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參數(shù)資料
| 型號： | XRT73LC00AIV |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 26/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU STS1/DS3/E3 SGL 44TQFP |
| 標準包裝： | 160 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應商設備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
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XRT73LC00A
29
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
2.4.2
Disabling the Transmit Line Build-Out Circuit
If the Transmit Line Build-Out circuit is disabled, then the XRT73LC00A outputs partially-shaped pulses onto
the line via the TTIP and TRING output pins.
Disable the Transmit Line Build-Out circuit in the XRT73LC00A by doing the following:
If the XRT73LC00A is operating in the Hardware Mode, set the TXLEV input pin (pin 1) to “High”
If the XRT73LC00A is operating in the HOST Mode, set the TXLEV bit-field to “1” as illustrated below.
2.4.3
Design Guideline for Setting the Transmit Line Build-Out Circuit
The setting ofTXLEV input pin or bit-field should be based upon the overall cable length between the
Transmitting Terminal and the Digital Cross Connect system where the pulse template measurements are
made.
If the cable length between the Transmitting Terminal and the DSX-3 or STSX-1 is less than 225 feet, it is
advisable to enable the Transmit Line Build-Out circuit by setting the TXLEV input pin or bit-field to "0".
NOTE: In this case the XRT73LC00A outputs shaped (e.g., not square-wave) pulses onto the line via the TTIP and TRING
output pins. The shape of this output pulse is such that it complies with the pulse template requirements even
when subjected to cable loss ranging from 0 to 225 feet.
If the cable length between the Transmitting
Terminal and the DSX-3 or STSX-1 is greater than 225 feet, it is advisable to disable the Transmit Line Build-
Out circuit by setting the TXLEV input pin or bit-field to "1".
NOTE: In this case the XRT73LC00A outputs partially-shaped pulses onto the line via the TTIP and TRING output pins.
The cable loss that these pulses experience over long cable lengths (e.g., greater than 225 feet) causes these
pulses to be properly shaped and comply with the appropriate pulse template requirement.
2.4.4
The Transmit Line Build-Out Circuit and E3 Applications
The ITU-T G.703 Pulse Template Requirements for E3 states that the E3 transmit output pulse should be
measured at the Secondary Side of the Transmit Output Transformer for Pulse Template compliance. There is
no Digital Cross Connect System pulse template requirement for E3 and the Transmit Line Build-Out circuit in
the XRT73LC00A is disabled whenever it is operating in the E3 Mode.
2.5
Interfacing the Transmit Section of the XRT73LC00A to the Line
The E3, DS3 and SONET STS-1 specification documents all state that line signals transmitted over coaxial
cable are to be terminated with 75 Ohms. Therefore, interface the Transmit Section of the XRT73LC00A, as
illustrated in Figure 16 which shows two 31.6 Ohm resistors in series with the primary side of the transformer.
These two 31.6Ohm resistors closely match the 75Ohm load termination resistor thereby minimizing Transmit
Return Loss.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4
D3
D2
D1
D0
TXOFF
TAOS
TXCLKINV
TXLEV
TXBIN
0
X
1
X
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73LC00AIV-F | 功能描述:外圍驅動器與原件 - PCI 1-Ch DS3, E3, SONET RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73LC00AIVTR | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00AIVTR-F | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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