參數(shù)資料
型號(hào)： XRT73LC00AIV
廠商： Exar Corporation
文件頁(yè)數(shù)： 43/61頁(yè)
文件大?。?/td> 0K
描述： IC LIU STS1/DS3/E3 SGL 44TQFP
標(biāo)準(zhǔn)包裝： 160
類(lèi)型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 托盤(pán)
XRT73LC00A
45
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
If the XRT73LC00A is operating in the HOST Mode:
Access the Microprocessor Serial Interface and write a “1” into the LLB bit-field and a “0” into the RLB bit-field
in Command Register 4.
If the XRT73LC00A is operating in the Hardware Mode:
The LLB input pin (pin 14) must be set to “High” and the RLB input pin (pin 15) must be set to “Low”.
NOTES:
1.
The Analog Local Loop-Back Mode does not work if the transmitter is turned off via the TXOFF feature.
2.
The XRT73LC00A automatically Declares an LOS Condition anytime it has been configured to operate in either
the Analog Local Loop-Back or Digital Local Loop-Back Modes. Consequently, the Muting -upon -LOS must be
disabled prior to configuring the device to operate in either of these local Loop-Back modes.
4.2
The Digital Local Loop-Back Mode
When the XRT73LC00A is configured to operate in the Digital Local Loop-Back Mode, it ignores any signals
that are input to the RTIP and RRING input pins. The Transmitting Terminal Equipment transmits clock and
data into the XRT73LC00A via the TPDATA, TNDATA and TCLK input pins. This data is processed through the
Transmit Clock Duty Cycle Adjust PLL and the HDB3/B3ZS Encoder block and then looped back to the HDB3/
B3ZS Decoder block.
Figure 30 illustrates the path that the data takes when the chip is configured to operate in the Digital Local
Loop-Back Mode.
FIGURE 29. THE ANALOG LOCAL LOOP-BACK IN THE XRT73LC00A
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
1
0
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
RTIP
RRING
REQDIS
RCLK1
RCLK2
RPOS
RNEG
DR/SR
RLOS
LLB
RLB
ENDECDIS
TAOS
TPDATA
TNDATA
TCLK
RLOL EXCLK
Device
Monitor
MTIP
MRING
Transmit
Logic
Duty Cycle Adjust
TXLEV
TXOFF
DMO
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Analog Local
Loop-Back Path
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XRT73LC00IV 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73LC03A 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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