參數(shù)資料
型號(hào): XRT75L00D
廠商: Exar Corporation
英文描述: E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER
文件頁(yè)數(shù): 43/92頁(yè)
文件大?。?/td> 894K
代理商: XRT75L00D
XRT75L00D
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
38
0x01
R/W
D0
DMOIE
Writing a “1” to this bit field enables the DMO inter-
rupt and triggers an interrupt when the transmitter
driver fails. Writing a “0” disables the interrupt.
0
D1
RLOSIE
Writing a “1” to this bit field enables the RLOS inter-
rupt and triggers an interrupt when the RLOS condi-
tion occurs. Writing a “0” disables the interrupt.
0
D2
RLOLIE
Writing a “1” to this bit field enables the RLOL inter-
rupt and triggers an interrupt when RLOL condition
occurs. Writing a “0” disables the interrupt.
0
D3
FLIE
Writing a “1” to this bit field enables the FL interrupt
and triggers an interrupt when the FIFO Limit of the
Jitter Attenuator is within 2 bits of overflow/underflow
condition. Writing a “0” disables the interrupt.
N
OTE
:
This bit field is ignored when the Jitter
Attenuator is disabled.
0
D4
PRBSIE
Writing a “1” to this bit enables the PRBS bit error
interrupt.
0
D5
CNT_SATIE
Writing a “1” to this bit enables the PRBS error-
counter saturation interrupt. When the PRBS error
counter reaches 0xFFFF, an interrupt will be gener-
ated.
0
0x02
Reset
Upon
Read
D0
DMOIS
This bit is set to “1” every time a DMO status change
has occurred since the last cleared interrupt.This bit
is cleared when read.
0
D1
RLOSIS
This bit is set to “1” every time a RLOS status change
has occurred since the last cleared interrupt. This bit
is cleared when read.
0
D2
RLOLIS
This bit is set to “1” every time a RLOL status change
has occurred since the last cleared interrupt. This bit
is cleared when read.
0
D3
FLIS
This bit is set to “1” every time a FIFO Limit status
change has occurred since the last cleared interrupt.
This bit is cleared when read.
0
D4
PRBSIS
This bit is set to “1” when a PRBS bit error is
detected. This bit is cleared when read.
0
D5
CNT_SATIS
This bit is set to “1” when the PRBS error counter has
saturated (0xFFFF). This bit is cleared when read.
0
T
ABLE
16: R
EGISTER
M
AP
D
ESCRIPTION
A
DDRESS
(H
EX
)
T
YPE
B
IT
L
OCATION
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
(B
IN
)
相關(guān)PDF資料
PDF描述
XRT75L00DIV E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L02 TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L02IV TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L04D FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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