參數(shù)資料
型號(hào): XRT75L00D
廠商: Exar Corporation
英文描述: E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER
文件頁(yè)數(shù): 44/92頁(yè)
文件大?。?/td> 894K
代理商: XRT75L00D
XRT75L00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.2
39
0x03
Read
Only
D0
DMO
This bit is set to “1” every time the MTIP/MRing input
pins have not detected any bipolar pulses for 128
consecutive bit periods.
0
D1
RLOS
This bit is set to “1” every time the receiver declares
an LOS condition.
0
D2
RLOL
This bit is set to “1” every time when the receiver
declares a Loss of Lock condition.
0
D3
FL
This bit is set to “1” every time the FIFO in the Jitter
Attenuator is within 2 bit of underflow/overflow condi-
tion.
0
D4
ALOS
This bit is set to “1” every time the receiver declares
Analog LOS condition.
0
D5
DLOS
This bit is set to “1” every time the receiver declares
Digital LOS condition.
0
D6
PRBSLS
This bit is set to “1” every time the PRBS detects a bit
error.
0
0x04
R/W
D0
TxLEV
Writing a “1” to this bit disables the Transmit Build-out
circuit and writing a “0” enables the Transmit Build-out
circuit.
N
OTE
:
See section 4.03 for detailed description.
0
D1
TxClkINV
Writing a “1” to this bit configures the transmitter to
sample the data on TPData/TNData input pins on the
rising edge of TxClk.
0
D2
TAOS
Setting this bit to “1” causes a continuous stream of
marks to be sent out at the TTIP and TRing pins.
0
D3
Reserved
This Bit Location is Not Used.
D4
INSPRBS
Writing a “1” to this bit causes the PRBS generator to
insert a single-bit error onto the transmit PRBS data
stream.
N
OTE
:
PRBS Generator/Detector must be enabled
for this bit to have any effect.
0
D5
TxMON
When this bit is set to “1”, the driver monitor is con-
nected to its own transmit channel and monitors the
transmit driver. When a transmit failure is detected,
the DMO output will go high.
When this bit is “0”, MTIP and MRing can be con-
nected to other transmit channel for monitoring.
0
T
ABLE
16: R
EGISTER
M
AP
D
ESCRIPTION
A
DDRESS
(H
EX
)
T
YPE
B
IT
L
OCATION
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
(B
IN
)
相關(guān)PDF資料
PDF描述
XRT75L00DIV E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L02 TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L02IV TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L04D FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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