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| 型號： | XRT75L00D |
| 廠商： | Exar Corporation |
| 英文描述： | E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| 中文描述： | E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER |
| 文件頁數(shù)： | 7/92頁 |
| 文件大小： | 894K |
| 代理商： | XRT75L00D |
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XRT75L00D
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
3
F
IGURE
38. A S
IMPLE
I
LLUSTRATION
OF
A
DS3 D
ATA
-S
TREAM
BEING
M
APPED
INTO
AN
STS-1 SPE,
VIA
A
PTE.............................. 57
9.2.2.2 T
HE
44.736M
BPS
+ 1
PPM
C
ASE
........................................................................................................................... 58
F
IGURE
39. A
N
I
LLUSTRATION
OF
THE
STS-1 SPE
TRAFFIC
THAT
WILL
BE
GENERATED
BY
THE
"S
OURCE
" PTE,
WHEN
MAPPING
IN
A
DS3
SIGNAL
THAT
HAS
A
BIT
RATE
OF
44.736M
BPS
+ 1
PPM
,
INTO
AN
STS-1
SIGNAL
................................................................ 58
9.2.2.3 T
HE
44.736M
BPS
- 1
PPM
C
ASE
............................................................................................................................ 59
9.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS .............................................................................. 60
9.3.1 THE CONCEPT OF AN STS-1 SPE POINTER........................................................................................................... 60
F
IGURE
40. A
N
I
LLUSTRATION
OF
THE
STS-1 SPE
TRAFFIC
THAT
WILL
BE
GENERATED
BY
THE
S
OURCE
PTE,
WHEN
MAPPING
A
DS3
SIGNAL
THAT
HAS
A
BIT
RATE
OF
44.736M
BPS
- 1
PPM
,
INTO
AN
STS-1
SIGNAL
............................................................................ 60
F
IGURE
41. A
N
I
LLUSTRATION
OF
AN
STS-1 SPE
STRADDLING
ACROSS
TWO
CONSECUTIVE
STS-1
FRAMES
.................................... 61
9.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK.................................................................................. 62
F
IGURE
42. T
HE
B
IT
-
FORMAT
OF
THE
16-B
IT
W
ORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
10
BITS
,
REFLECTING
THE
LOCATION
OF
THE
J1
BYTE
,
DESIGNATED
......................................................................................................................................... 62
F
IGURE
43. T
HE
R
ELATIONSHIP
BETWEEN
THE
C
ONTENTS
OF
THE
"P
OINTER
B
ITS
" (
E
.
G
.,
THE
10-
BIT
EXPRESSION
WITHIN
THE
H1
AND
H2
BYTES
)
AND
THE
L
OCATION
OF
THE
J1 B
YTE
WITHIN
THE
E
NVELOPE
C
APACITY
OF
AN
STS-1 F
RAME
................................ 62
9.3.3 CAUSES OF POINTER ADJUSTMENTS................................................................................................................... 63
F
IGURE
44. A
N
I
LLUSTRATION
OF
AN
STS-1
SIGNAL
BEING
PROCESSED
VIA
A
S
LIP
B
UFFER
............................................................. 64
F
IGURE
45. A
N
I
LLUSTRATION
OF
THE
B
IT
F
ORMAT
WITHIN
THE
16-
BIT
WORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
"I"
BITS
DESIGNATED
................................................................................................................................................................... 65
F
IGURE
46. A
N
I
LLUSTRATION
OF
THE
B
IT
-F
ORMAT
WITHIN
THE
16-
BIT
WORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
"D"
BITS
DESIGNATED
................................................................................................................................................................... 66
9.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS ............................................................................... 67
9.4 CLOCK GAPPING JITTER ............................................................................................................................. 67
F
IGURE
47. I
LLUSTRATION
OF
THE
T
YPICAL
A
PPLICATIONS
FOR
THE
LIU
IN
A
SONET D
E
-S
YNC
A
PPLICATION
.................................. 67
9.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE)
FOR DS3 APPLICATIONS ............................................................................................................................ 68
T
ABLE
18: S
UMMARY
OF
"C
ATEGORY
I I
NTRINSIC
J
ITTER
R
EQUIREMENT
PER
T
ELCORDIA
GR-253-CORE,
FOR
DS3
APPLICATIONS
.. 68
9.5.1 DS3 DE-MAPPING JITTER......................................................................................................................................... 69
9.5.2 SINGLE POINTER ADJUSTMENT............................................................................................................................. 69
9.5.3 POINTER BURST........................................................................................................................................................ 69
F
IGURE
48. I
LLUSTRATION
OF
S
INGLE
P
OINTER
A
DJUSTMENT
S
CENARIO
......................................................................................... 69
9.5.4 PHASE TRANSIENTS................................................................................................................................................. 70
F
IGURE
49. I
LLUSTRATION
OF
B
URST
OF
P
OINTER
A
DJUSTMENT
S
CENARIO
..................................................................................... 70
F
IGURE
50. I
LLUSTRATION
OF
"P
HASE
-T
RANSIENT
" P
OINTER
A
DJUSTMENT
S
CENARIO
..................................................................... 70
9.5.5 87-3 PATTERN............................................................................................................................................................ 71
9.5.6 87-3 ADD..................................................................................................................................................................... 71
F
IGURE
51. A
N
I
LLUSTRATION
OF
THE
87-3 C
ONTINUOUS
P
OINTER
A
DJUSTMENT
P
ATTERN
............................................................. 71
9.5.7 87-3 CANCEL.............................................................................................................................................................. 72
F
IGURE
52. I
LLUSTRATION
OF
THE
87-3 A
DD
P
OINTER
A
DJUSTMENT
P
ATTERN
................................................................................ 72
F
IGURE
53. I
LLUSTRATION
OF
87-3 C
ANCEL
P
OINTER
A
DJUSTMENT
S
CENARIO
................................................................................ 72
9.5.8 CONTINUOUS PATTERN........................................................................................................................................... 73
9.5.9 CONTINUOUS ADD................................................................................................................................................... 73
F
IGURE
54. I
LLUSTRATION
OF
C
ONTINUOUS
P
ERIODIC
P
OINTER
A
DJUSTMENT
S
CENARIO
................................................................ 73
9.5.10 CONTINUOUS CANCEL........................................................................................................................................... 74
F
IGURE
55. I
LLUSTRATION
OF
C
ONTINUOUS
-A
DD
P
OINTER
A
DJUSTMENT
S
CENARIO
........................................................................ 74
F
IGURE
56. I
LLUSTRATION
OF
C
ONTINUOUS
-C
ANCEL
P
OINTER
A
DJUSTMENT
S
CENARIO
................................................................... 74
9.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ................................. 75
9.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM
APPLICATION ............................................................................................................................................... 75
9.7.1 INTRINSIC JITTER TEST RESULTS.......................................................................................................................... 75
T
ABLE
19: S
UMMARY
OF
"C
ATEGORY
I I
NTRINSIC
J
ITTER
T
EST
R
ESULTS
"
FOR
SONET/DS3 A
PPLICATIONS
..................................... 75
9.7.2 WANDER MEASUREMENT TEST RESULTS............................................................................................................ 76
9.8 DESIGNING WITH THE LIU ........................................................................................................................... 76
9.8.1 HOW TO DESIGN AND CONFIGURE THE LIU TO PERMIT A SYSTEM TO MEET THE ABOVE-MENTIONED INTRIN-
SIC JITTER AND WANDER REQUIREMENTS ............................................................................................................ 76
F
IGURE
57. I
LLUSTRATION
OF
THE
LIU
BEING
CONNECTED
TO
A
M
APPER
IC
FOR
SONET D
E
-S
YNC
A
PPLICATIONS
.......................... 76
C
HANNEL
C
ONTROL
R
EGISTER
.....................................................................................................................77
C
HANNEL
C
ONTROL
R
EGISTER
.....................................................................................................................78
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
....................................................................................................78
9.8.2 RECOMMENDATIONS ON PRE-PROCESSING THE GAPPED CLOCKS (FROM THE MAPPER/ASIC DEVICE) PRIOR
TO ROUTING THIS DS3 CLOCK AND DATA-SIGNALS TO THE TRANSMIT INPUTS OF THE LIU ........................ 79
9.8.2.1 SOME NOTES PRIOR TO STARTING THIS DISCUSSION: ............................................................................ 79
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
....................................................................................................79
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
....................................................................................................79
9.8.2.2 OUR PRE-PROCESSING RECOMMENDATIONS ............................................................................................ 80
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| XRT75L00DIV | E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XRT75L00DES | 功能描述:時鐘合成器/抖動清除器 LIU+DESYNCH 3.3V LIU+DESYNCH 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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| XRT75L00DIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI 1-Ch DS3, E3, SONET RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75L00DIVTR | 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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