參數(shù)資料
型號: XRT75L03D
廠商: Exar Corporation
英文描述: THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: Three頻道E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER
文件頁數(shù): 51/134頁
文件大?。?/td> 659K
代理商: XRT75L03D
á
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L03D
REV. 1.0.0
46
5.2
The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream
and provides the retimed data to the B3ZS (HDB3) decoder.
The Clock Recovery PLL can be in one of the following two modes:
T
RAINING
M
ODE
:
In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the
recovered line clock signal and the reference clock applied on the ExClk_n input pins exceed 0.5%, a Loss of
Lock condition is declared by toggling RLOL_n output pin “High” (in Hardware Mode) or setting the RLOL_n bit
to “1” in the control registers (in Host Mode). Also, the clock output on the RxClk_n pins are the same as the
reference clock applied on ExClk_n pins.
D
ATA
/C
LOCK
R
ECOVERY
M
ODE
:
In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference
between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on
the RxClk_n out pins is the Recovered Clock signal.
Clock and Data Recovery:
F
IGURE
18. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
E3.
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
M
ODE
C
ABLE
L
ENGTH
(A
TTENUATION
)
I
NTERFERENCE
T
OLERANCE
E3
0 dB
Equalizer “IN”
-17 dB
12 dB
-14 gB
DS3
0 feet
-15 dB
225 feet
-15 dB
450 feet
-14 dB
STS-1
0 feet
-15 dB
225 feet
-14 dB
450 feet
-14 dB
Test Equipment
Noise Generator
2
23
-1 PRBS
Signal Source
N
S
0 to 12 dB Cable Loss
DUT
XRT75L03D
Attenuator 1
Attenuator 2
相關(guān)PDF資料
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