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參數(shù)資料
| 型號(hào)： | XRT75R03DIV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP128 |
| 封裝： | 14 X 20 MM, LQFP-128 |
| 文件頁(yè)數(shù)： | 56/134頁(yè) |
| 文件大?。?/td> | 803K |
| 代理商： | XRT75R03DIV |
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XRT75R03D
REV. 1.0.2
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
51
7.2
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input
versus frequency.
There are two distinct characteristics in jitter transfer: jitter gain (jitter peaking) defined as the highest ratio
above 0dB; and jitter transfer bandwidth.The overall jitter transfer bandwidth is controlled by a low bandwidth
loop, typically using a voltage-controller crystal oscillator (VCXO).
The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often
expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer
indicates the element added jitter.A zero dB jitter transfer indicates the element had no effect on jitter.
Table 12 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates:
J
ITTER
T
RANSFER
- R
ECEIVER
/T
RANSMITTER
:
The above specifications can be met only with a jitter attenuator that supports E3/DS3/STS-1 rates.
7.3
Jitter Attenuator:
An advanced crystal-less jitter attenuator per channel is included in the XRT75R03D. The jitter attenuator
requires no external crystal nor high-frequency reference clock.
In Host mode, by clearing or setting the JATx/Rx_n bits in the channel control registers selects the jitter
attenuator either in the Receive or Transmit path on per channel basis. In Hardware mode, JATx/Rx pin selects
globally all three channels either in Receive or Transmit path.
The FIFO size can be either 16-bit or 32-bit. In HOST mode, the bits JA0_n and JA1_n can be set to
appropriate combination to select the different FIFO sizes or to disable the Jitter Attenuator on a per channel
basis. In Hardware mode, appropriate setting of the pins JA0 and JA1 selects the different FIFO sizes or
disables the Jitter Attenuator for all three channels. Data is clocked into the FIFO with the associated clock
signal (TxClk or RxClk) and clocked out of the FIFO with the dejittered clock. When the FIFO is within two bits
of overflowing or underflowing, the FIFO limit status bit, FL_n is set to “1” in the Alarm status register. Reading
this bit clears the FIFO and resets the bit into default state.
N
OTE
:
It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts
of jitter. Table 13 specifies the jitter transfer mask requirements for various data rates:
T
ABLE
11: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
)
B
IT
R
ATE
(
KB
/
S
)
S
TANDARD
I
NPUT
J
ITTER
A
MPLITUDE
(UI
P
-
P
)
M
ODULATION
F
REQUENCY
A1
A2
A3
F
1(H
Z
)
F
2(H
Z
)
F
3(
K
H
Z
)
F
4(
K
H
Z
)
F
5(
K
H
Z
)
34368
ITU-T G.823
1.5
0.15
-
100
1000
10
800
-
44736
GR-499
CORE Cat I
5
0.1
-
10
2.3k
60
300
-
44736
GR-499
CORE Cat II
10
0.3
-
10
669
22.3
300
-
51840
GR-253
CORE Cat II
15
1.5
0.15
10
30
300
2
20
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
E3
DS3
STS-1
ETSI TBR-24
GR-499 CORE section 7.3.2
Category I and Category II
GR-253 CORE section 5.6.2.1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT75R03 | THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75R03IV | THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75R06D | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| XRT75R06DIB | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| XRT75R06 | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75R03DIV-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3-Ch E3/DS3/STS-1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT75R03DIVTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75R03DIVTR-F | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| XRT75R03ES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75R03IV | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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