參數(shù)資料
型號： XRT75R03DIV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
中文描述： DATACOM, PCM TRANSCEIVER, PQFP128
封裝： 14 X 20 MM, LQFP-128
文件頁數(shù)： 96/134頁
文件大?。?/td> 803K
代理商： XRT75R03DIV
XRT75R03D
REV. 1.0.2
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
91
In general, there are three (3) sources of Jitter and Wander within an asynchronously-mapped DS3 signal that
the system designer must be aware of. These sources are listed below.
Mapping/De-Mapping Jitter
Pointer Adjustments
Clock Gapping
Each of these sources of jitter/wander will be defined and discussed in considerable detail within this Section.
In order to accomplish all of this, this particular section will discuss all of the following topics in details.
How DS3 data is mapped into SONET, and how this mapping operation contributes to Jitter and Wander
within this "eventually de-mapped" DS3 signal.
How this asynchronously-mapped DS3 data is transported throughout the SONET Network, and how
occurrences on the SONET network (such as pointer adjustments) will further contributes to Jitter and
Wander within the "eventually de-mapped" DS3 signal.
A review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications
A review of the DS3 Wander requirements per ANSI T1.105.03b-1997
A review of the Intrinsic Jitter and Wander Capabilities of the XRT75R03D in a typical system application
An in-depth discussion on how to design with and configure the XRT75R03D to permit the system to the
meet the above-mentioned Intrinsic Jitter and Wander requirements
N
OTE
:
An in-depth discussion on SDH De-Sync Applications will be presented in the next revision of this data sheet.
10.2
MAPPING/DE-MAPPING JITTER/WANDER
Mapping/De-Mapping Jitter (or Wander) is defined as that intrinsic jitter (or wander) that is induced into a DS3
signal by the "Asynchronous Mapping" process. This section will discuss all of the following aspects of
Mapping/De-Mapping Jitter.
How DS3 data is mapped into an STS-1 SPE
How frequency offsets within either the DS3 signal (being mapped into SONET) or within the STS-1 signal
itself contributes to intrinsic jitter/wander within the DS3 signal (being transported via the SONET network).
10.2.1
HOW DS3 DATA IS MAPPED INTO SONET
Whenever a DS3 signal is asynchronously mapped into SONET, this mapping is typically accomplished by a
PTE accepting DS3 data (from some remote terminal) and then loading this data into certain bit-fields within a
given STS-1 SPE (or Synchronous Payload Envelope). At this point, this DS3 signal has now been
asynchronously mapped into an STS-1 signal. In most applications, the SONET Network will then take this
particular STS-1 signal and will map it into "higher-speed" SONET signals (e.g., STS-3, STS-12, STS-48, etc.)
and will then transport this asynchronously mapped DS3 signal across the SONET network, in this manner. As
this "asynchronously-mapped" DS3 signal approaches its "destination" PTE, this STS-1 signal will eventually
be de-mapped from this STS-N signal. Finally, once this STS-1 signal reaches the "destination" PTE, then this
asynchronously-mapped DS3 signal will be extracted from this STS-1 signal.
10.2.1.1
A Brief Description of an STS-1 Frame
In order to be able to describe how a DS3 signal is asynchronously mapped into an STS-1 SPE, it is important
to define and understand all of the following.
The STS-1 frame structure
The STS-1 SPE (Synchronous Payload Envelope)
Telcordia GR-253-CORE’s recommendation on mapping DS3 data into an STS-1 SPE
An STS-1 frame is a data-structure that consists of 810 bytes (or 6480 bits). A given STS-1 frame can be
viewed as being a 9 row by 90 byte column array (making up the 810 bytes). The frame-repetition rate (for an
STS-1 frame) is 8000 frames/second. Therefore, the bit-rate for an STS-1 signal is (6480 bits/frame * 8000
frames/sec =) 51.84Mbps.
相關(guān)PDF資料
PDF描述
XRT75R03 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R03IV THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R06DIB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75R03DIV-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3-Ch E3/DS3/STS-1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT75R03DIVTR 功能描述:時鐘合成器/抖動清除器 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R03DIVTR-F 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
XRT75R03ES 功能描述:時鐘合成器/抖動清除器 3CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R03IV 功能描述:外圍驅(qū)動器與原件 - PCI 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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