參數(shù)資料
型號: XRT75R12DIB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: DATACOM, PCM TRANSCEIVER, PBGA420
封裝: 35 X 35 MM, TBGA-420
文件頁數(shù): 121/131頁
文件大?。?/td> 717K
代理商: XRT75R12DIB
PRELIMINARY
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. P1.0.1
116
If the LIU has been configured to operate in the Hardware Mode
Then the user should tie pin 65 (SR/DR*) to "High".
c. Configure each of the channels within the LIU to operate in the SONET De-Sync Mode
The user can accomplish this by executing either of the following steps.
If the LIU has been configured to operate in the Host Mode.
Then the user should set Bit D2 (JA0) to "0" and Bit D0 (JA1) to "1", within the Jitter Attenuator Control
Register, as depicted below.
If the LIU has been configured to operate in the Hardware Mode
Then the user should tie pin 44 (JA0) to a logic "HIGH" and pin 42 (JA1) to a logic "LOW".
Once the user accomplishes either of these steps, then the Jitter Attenuator (within the LIU) will be configured
to operate with a very narrow bandwidth.
d. Configure the Jitter Attenuator (within each of the channels) to operate in the Transmit Direction.
The user can accomplish this by executing either the following steps.
If the LIU has been configured to operate in the Host Mode.
Then the user should be Bit D1 (JATx/JARx*) to "1", within the Jitter Attenuator Control Register, as depicted
below.
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06
CHANNEL 1 ADDRESS LOCATION = 0X0E
CHANNEL 2 ADDRESS LOCATION = 0X16
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
PRBS Enable
Ch_n
RLB_n
LLB_n
E3_n
STS-1/
DS3
_n
SR/DR_n
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
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