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參數(shù)資料
| 型號(hào)： | XRT75R12DIB |
| 廠商： | EXAR CORP |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA420 |
| 封裝： | 35 X 35 MM, TBGA-420 |
| 文件頁(yè)數(shù)： | 90/131頁(yè) |
| 文件大?。?/td> | 717K |
| 代理商： | XRT75R12DIB |
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XRT75R12D
REV. P1.0.1
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
PRELIMINARY
85
8.0
THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU
The LIU with D-SYNC is very similar to the non D-SYNC LIU in that they both contain Jitter Attenuator blocks
within each channel. They are also pin to pin compatible with each other. However, the Jitter Attenuators
within the D-SYNC have some enhancements over and above those within the non D-SYNC device. The Jitter
Attenuator blocks will support all of the modes and features that exist in the non D-SYNC device and in
addition they also support a SONET/SDH De-Sync Mode.
N
OTE
:
The "D" suffix within the part number stands for "De-Sync".
The SONET/SDH De-Sync feature of the Jitter Attenuator blocks permits the user to design a SONET/SDH
PTE (Path Terminating Equipment) that will comply with all of the following Intrinsic Jitter and Wander
requirements.
For SONET Applications
I
Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 Applications)
I
ANSI T1.105.03b-1997 - SONET Jitter at Network Interfaces - DS3 Wander Supplement
For SDH Applications
I
Jitter and Wander Generation Requirements per ITU-T G.783 (for DS3 and E3 Applications)
Specifically, if the user designs in the LIU along with a SONET/SDH Mapper IC (which can be realized as
either a standard product or as a custom logic solution, in an ASIC or FPGA), then the following can be
accomplished.
The Mapper can receive an STS-N or an STM-M signal (which is carrying asynchronously-mapped DS3 and/
or E3 signals) and byte de-interleave this data into N STS-1 or 3*M VC-3 signals
The Mapper will then terminate these STS-1 or VC-3 signals and will de-map out this DS3 or E3 data from
the incoming STS-1 SPEs or VC-3s, and output this DS3 or E3 to the DS3/E3 Facility-side towards the LIU
This DS3 or E3 signal (as it is output from these Mapper devices) will contain a large amount of intrinsic jitter
and wander due to (1) the process of asynchronously mapping a DS3 or E3 signal into a SONET or SDH
signal, (2) the occurrence of Pointer Adjustments within the SONET or SDH signal (transporting these DS3
or E3 signals) as it traverses the SONET/SDH network, and (3) clock gapping.
When the LIU has been configured to operate in the "SONET/SDH De-Sync" Mode, then it will (1) accept this
jittery DS3 or E3 clock and data signal from the Mapper device (via the Transmit System-side interface) and
(2) through the Jitter Attenuator, the LIU will reduce the Jitter and Wander amplitude within these DS3 or E3
signals such that they (when output onto the line) will comply with the above-mentioned intrinsic jitter and
wander specifications.
8.1
BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS
This section provides an in-depth discussion on the mechanisms that will cause Jitter and Wander within a
DS3 or E3 signal that is being transported across a SONET or SDH Network. A lot of this material is
introductory, and can be skipped by the engineer that is already experienced in SONET/SDH designs.
In the wide-area network (WAN) in North America it is often necessary to transport a DS3 signal over a long
distance (perhaps over a thousand miles) in order to support a particular service. Now rather than realizing
this transport of DS3 data, by using over a thousand miles of coaxial cable (interspaced by a large number of
DS3 repeaters) a common thing to do is to route this DS3 signal to a piece of equipment (such as a Terminal
MUX, which in the "SONET Community" is known as a PTE or Path Terminating Equipment). This Terminal
MUX will asynchronously map the DS3 signal into a SONET signal. At this point, the SONET network will now
transport this asynchronously mapped DS3 signal from one PTE to another PTE (which is located at the other
end of the SONET network). Once this SONET signal arrives at the remote PTE, this DS3 signal will then be
extracted from the SONET signal, and will be output to some other DS3 Terminal Equipment for further
processing.
Similar things are done outside of North America. In this case, this DS3 or E3 signal is routed to a PTE, where
it is asynchronously mapped into an SDH signal. This asynchronously mapped DS3 or E3 signal is then
transported across the SDH network (from one PTE to the PTE at the other end of the SDH network). Once
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| XRT75R12DIB-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT75R12DIB-L | 功能描述:LIN 收發(fā)器 Synch RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8 |
| XRT75R12ES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 12CH T3/E3/STS1LIUJA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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