參數(shù)資料
型號: XRT75R12DIB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: DATACOM, PCM TRANSCEIVER, PBGA420
封裝: 35 X 35 MM, TBGA-420
文件頁數(shù): 73/131頁
文件大?。?/td> 717K
代理商: XRT75R12DIB
PRELIMINARY
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. P1.0.1
68
T
ABLE
28: XRT75R12D R
EGISTER
MAP
SHOWING
I
NTERRUPT
S
TATUS
R
EGISTERS
(ISR_
N
)
T
ABLE
29: S
OURCE
L
EVEL
NTERRUPT
S
TATUS
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
2
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Reserved
Change of FL
Condition
Interrupt Status
Ch_n
Change of LOL
Condition
Interrupt Status
Ch_n
Change of LOS
Condition
nterrupt Status
Ch_n
Change of DMO
Condition
Interrupt Status
Ch_n
RUR
RUR
RUR
RUR
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
7 - 4
Reserved
3
Change of FL Con-
dition Interrupt Sta-
tus
RUR
Change of FL (FIFO Limit Alarm) Condition Interrupt Status - Ch n:
This RESET-upon-READ bit-field indicates whether or not the Change
of FL Condition Interrupt (for Channel n) has occurred since the last
read of this register.
0 - Indicates that the Change of FL Condition Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the Change of FL Condition Interrupt has occurred
since the last read of this register.
N
OTE
:
The user can determine the current state of the FIFO Alarm
condition by reading out the contents of Bit 3 (FL Alarm
Declared) within the Alarm Status Register.(n)
2
Change of LOL
Condition Interrupt
Status
RUR
Change of Receive LOL (Loss of Lock) Condition Interrupt Status
- Ch n:
This RESET-upon-READ bit-field indicates whether or not the Change
of Receive LOL Condition Interrupt (for Channel n) has occurred since
the last read of this register.
0 - Indicates that the Change of Receive LOL Condition Interrupt has
NOT occurred since the last read of this register.
1 - Indicates that the Change of Receive LOL Condition Interrupt has
occurred since the last read of this register.
N
OTE
:
The user can determine the current state of the Receive LOL
Defect condition by reading out the contents of Bit 2 (Receive
LOL Defect Declared) within the Alarm Status Register.(n)
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