參數(shù)資料
型號(hào): XRT75R12DIB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: DATACOM, PCM TRANSCEIVER, PBGA420
封裝: 35 X 35 MM, TBGA-420
文件頁(yè)數(shù): 76/131頁(yè)
文件大?。?/td> 717K
代理商: XRT75R12DIB
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)當(dāng)前第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)
XRT75R12D
REV. P1.0.1
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
PRELIMINARY
71
5
Digital LOS Defect
Declared
R/O
Digital LOS Defect Declared:
This READ-ONLY bit-field indicates whether or not the Digital LOS
(Loss of Signal) detector is declaring the LOS Defect condition.
For DS3 and STS-1 applications, the Digital LOS Detector will declare
the LOS Defect condition whenever it detects an absence of pulses
(within the incoming DS3 or STS-1 data-stream) for 160 consecutive
bit-periods.
Further, (again for DS3 and STS-1 applications) the Digital LOS Detec-
tor will clear the LOS Defect condition whenever it determines that the
pulse density (within the incoming DS3 or STS-1 signal) is at least
33%.
0 - Indicates that the Digital LOS Detector is NOT declaring the LOS
Defect Condition.
1 - Indicates that the Digital LOS Detector is currently declaring the
LOS Defect condition.
N
OTES
:
1.
LOS Detection (within each channel of the XRT75R12D) is
performed by both an Analog LOS Detector and a Digital LOS
Detector. The LOS state of a given Channel is simply a
WIRED-OR of the LOS Defect Declare states of these two
detectors.
2.
The current LOS Defect Condition (for the channel) can be
determined by reading out the contents of Bit 1 (Receive LOS
Defect Declared) within this register.
4
Analog LOS Defect
Declared
R/O
Analog LOS Defect Declared:
This READ-ONLY bit-field indicates whether or not the Analog LOS
(Loss of Signal) detector is declaring the LOS Defect condition.
For DS3 and STS-1 applications, the Analog LOS Detector will declare
the LOS Defect condition whenever it determines that the amplitude of
the pulses (within the incoming DS3/STS-1 line signal) drops below a
certain Analog LOS Defect Declaration threshold level.
Conversely, (again for DS3 and STS-1 applications) the Analog LOS
Detector will clear the LOS Defect condition whenever it determines
that the amplitude of the pulses (within the incoming DS3/STS-1 line
signal) has risen above a certain Analog LOS Defect Clearance
threshold level.
It should be noted that, in order to prevent "chattering" within the Ana-
log LOS Detector output, there is some built-in hysteresis between the
Analog LOS Defect Declaration and the Analog LOS Defect Clearance
threshold levels.
0 - Indicates that the Analog LOS Detector is NOT declaring the LOS
Defect Condition.
1 - Indicates that the Analog LOS Detector is currently declaring the
LOS Defect condition.
N
OTES
:
1.
LOS Detection (within each channel of the XRT75R12D) is
performed by both an Analog LOS Detector and a Digital LOS
Detector. The LOS state of a given Channel is simply a
WIRED-OR of the LOS Defect Declare states of these two
detectors.
2.
The current LOS Defect Condition (for the channel) can be
determined by reading out the contents of Bit 1 (Receive LOS
Defect Declared) within this register.
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12IB TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00IV E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT79L71 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75R12DIB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT75R12DIB-L 功能描述:LIN 收發(fā)器 Synch RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT75R12ES 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 12CH T3/E3/STS1LIUJA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R12IB 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 12CH E3/DS3/STS W/JITTER R3 TECH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R12IB-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray