參數(shù)資料
型號: XRT75R12DIB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: DATACOM, PCM TRANSCEIVER, PBGA420
封裝: 35 X 35 MM, TBGA-420
文件頁數(shù): 45/131頁
文件大?。?/td> 717K
代理商: XRT75R12DIB
PRELIMINARY
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. P1.0.1
40
The jitter attenuator within the XRT75R12D meets the latest jitter attenuation specifications and/or jitter
transfer characteristics as shown in the Figure 28.
5.3.1
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in
the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and
data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is
essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set
according to the data rate. In general, the jitter is measured over a band of frequencies.
J
ITTER
G
ENERATION
T
ABLE
11: J
ITTER
T
RANSFER
P
ASS
M
ASKS
R
ATE
(
KBITS
)
M
ASK
F1
(H
Z
)
F2
(H
Z
)
F3
(H
Z
)
F4
(
K
H
Z
)
A1(dB)
A2(dB)
34368
G.823
ETSI-TBR-24
100
300
3
K
800
K
0.5
-19.5
44736
GR-499, Cat I
GR-499, Cat II
GR-253 CORE
10
10
10
10k
56.6k
40
-
-
-
15k
300k
15k
0.1
0.1
0.1
-
-
-
51840
GR-253 CORE
10
40k
-
400k
0.1
-
F
IGURE
28. J
ITTER
T
RANSFER
R
EQUIREMENTS
AND
J
ITTER
A
TTENUATOR
P
ERFORMANCE
F1
A1
F2
J
JITTER FREQ U ENCY (kHz)
A2
F3
F4
相關(guān)PDF資料
PDF描述
XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12IB TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00IV E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT79L71 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
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