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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PRELIMINARY
XRT79L71
REV. P1.0.3
255
2
Detection of Uncorrect-
able HEC Byte Error
Interrupt Status
RUR
Detection of Uncorrectable HEC Byte Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
"Receive ATM Cell Processor block" has declared the "Detection
of Uncorrectable HEC Byte Error" Interrupt since the last read of
this register.
The Receive ATM Cell Processor block will generate this inter-
rupt anytime it has received an ATM cell that contains an "uncor-
rectable" HEC byte error.
0 - Indicates that the Receive ATM Cell Processor block has
NOT declared the "Detection of Uncorrectable HEC Byte Error"
interrupt since the last read of this register.
1 - Indicates that the Receive ATM Cell Processor block has
declared the "Detection of Uncorrectable HEC Byte Error" Inter-
rupt since the last read of this register.
1
Clearance of LCD
Interrupt Status
RUR
Clearance of LCD (Loss of Cell Delineation) Defect Condi-
tion Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Receive ATM Cell Processor block has cleared the LCD Defect
condition since the last read of this register.
N
OTE
:
If the Receive ATM Cell Processor block clears the LCD
Defect, then this means that the Receive ATM Cell
Processor block is currently properly delineating ATM
cells that it receives from the Receive DS3/E3 Framer.
0 - Indicates that the Receive ATM Cell Processor block has
NOT cleared the LCD Defect since the last read of this register.
1 - Indicates that the Receive ATM Cell Processor block has
cleared the LCD Defect since the last read of this register.
0
Declaration of LCD
Interrupt Status
RUR
Declaration of LCD (Loss of Cell Delineation) Defect Condi-
tion Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
Receive ATM Cell Processor block has declared the LCD Defect
condition since the last read of this register.
N
OTE
:
If the Receive ATM Cell Processor block declares the
LCD Defect, then this means that the Receive ATM Cell
Processor block is NOT currently delineation ATM cells
that it receives from the Receive DS3/E3 Framer.
0 - Indicates that the Receive ATM Cell Processor block has
NOT declared the LCD Defect since the last read of this register.
1 - Indicates that the Receive ATM Cell Processor block has
declared the LCD Defect since the last read of this register.
RECEIVE ATM CELL PROCESSOR BLOCK - RECEIVE ATM INTERRUPT ENABLE REGISTER - BYTE 1
(ADDRESS = 0X170E)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Unused
Receive Cell
Extraction
Interrupt
Enable
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
0
0
0
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION