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1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PRELIMINARY
XRT79L71
REV. P1.0.3
341
TRANSMIT ATM CELL PROCESSOR BLOCK
This section presents the Register Description/Address Map of the control registers associated with the
Transmit ATM Cell Processor block.
T
ABLE
18: T
RANSMIT
ATM C
ELL
P
ROCESSOR
/PPP P
ACKET
P
ROCESSOR
B
LOCK
- R
EGISTER
/A
DDRESS
M
AP
A
DDRESS
L
OCATION
R
EGISTER
N
AME
T
YPE
D
EFAULT
V
ALUE
T
RANSMIT
ATM C
ELL
P
ROCESSOR
/PPP P
ROCESSOR
B
LOCK
C
ONTROL
R
EGISTERS
0x1F00
Transmit ATM Cell Processor Control Register - Byte 3
R/W
0x00
0x1F01
Transmit ATM Cell Processor Control Register - Byte 2
R/W
0x00
0x1F02
Transmit ATM Cell Processor Control Register - Byte 1
R/W
0x00
0x1F03
Transmit ATM Cell/PPP Processor Control Register - Byte 0
R/W
0x00
0x1F04 - 0x1F06
Reserved
R/O
0x00
0x1F07
Transmit ATM Status Register
R/O
0x00
0x1F05 - 0x1F0A
Reserved
R/O
0x00
0x1F0B
Transmit ATM Cell/PPP Processor Interrupt Status Register
RUR
0x00
0x1F0C - 0x1F0E
Reserved
R/O
0x00
0x1F0F
Transmit ATM Cell/PPP Processor Interrupt Enable Register
R/W
0x00
0x1F10 - 0x1F12
Reserved
R/O
0x00
0x1F13
Transmit ATM Cell Insertion/Extraction Memory Control Register
R/O & R/
W
0x00
0x1F14
Transmit ATM Cell Insertion/Extraction Memory - Byte 3
R/W
0x00
0x1F15
Transmit ATM Cell Insertion/Extraction Memory - Byte 2
R/W
0x00
0x1F16
Transmit ATM Cell Insertion/Extraction Memory - Byte 1
R/W
0x00
0x1F17
Transmit ATM Cell Insertion/Extraction Memory - Byte 0
R/W
0x00
0x1F18
Transmit ATM Cell - Idle Cell Header Byte # 1 Register
R/W
0x00
0x1F19
Transmit ATM Cell - Idle Cell Header Byte # 2 Register
R/W
0x00
0x1F1A
Transmit ATM Cell - Idle Cell Header Byte # 3 Register
R/W
0x00
0x1F1B
Transmit ATM Cell - Idle Cell Header Byte # 4 Register
R/W
0x00
0x1F1C - 0x1F1E
Reserved
R/O
0x00
0x1F1F
Transmit ATM Cell - Idle Cell Payload Byte Register
R/W
0x00
0x1F20
Transmit ATM Cell - Test Cell Header Byte # 1 Register
R/W
0x00
0x1F21
Transmit ATM Cell - Test Cell Header Byte # 2 Register
R/W
0x00
0x1F22
Transmit ATM Cell - Test Cell Header Byte # 3 Register
R/W
0x00
0x1F23
Transmit ATM Cell - Test Cell Header Byte # 4 Register
R/W
0x00
0x1F24 - 0x1F27
Reserved
R/O
0x00
0x1F28
Transmit ATM Cell - Cell Count Register - Byte 3
RUR
0x00