參數(shù)資料
型號： XRT79L73IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
中文描述： ATM NETWORK INTERFACE, PBGA456
封裝： 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-456
文件頁數(shù)： 33/71頁
文件大小： 495K
代理商： XRT79L73IB
t
3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PRELIMINARY
XRT79L73
REV. P1.0.0
31
N4
K22
R3
RxPOH_Clk1/
RxClk1/
RxNibClk1
RxPOH_Clk2/
RxClk2/
RxNibClk2
RxPOH_Clk3/
RxClk3/
RxNibClk3
O
O
O
Receive PLCP Path Overhead Serial Port Clock output/Receive Nibble-Par-
allel Output port clock/Receive Serial Clock output:
The function of these output pins depend upon whether the XRT79L73 has
been configured to operate in the ATM/PLCP Mode or the Clear-Channel
Framer Mode.
ATM/PLCP Mode - RxPOH_Clk:
These output clock pins along with RxPOH, RxPOHFrame and RxPOHIns pins
comprise the Receive PLCP Frame POH Byte serial output port. All POH (Path
Overhead) data that is output via the RxPOH output pin is updated on the rising
edge of these clock signals.
N
OTE
:
These output signals are inactive if the XRT79L73 has been configured
to operate in the Direct-Mapped ATM Mode.
Clear-Channel Framer Mode - RxClk:
These output pins are active whenever the XRT79L73 has been configured to
operate in either the Serial or Nibble Parallel Mode, as is described
below.Clear-Channel Framer/Serial Mode - RxClkIn this serial mode, these out-
puts are a 44.736MHz clock output signal (for DS3 applications) or 34.368MHz
clock output signal (for E3 applications). The Receive Payload Data Output
Interface will update the data via the RxSer output pin, upon the rising edge of
these clock signals.
The user is advised to design (or configure) the local terminal equipment to
sample the RxSer data, upon the falling edge of these clock signals.
Clear-Channel Framer/Nibble-Parallel Mode - RxNibClk:
In the Nibble-Parallel Mode, the XRT79L73 will derive these clock signals from
the RxLineClk signal. The XRT79L73 will pulse these clock signals 1176 times
for each inbound DS3 frame or 1074 times for each inbound E3/ITU-T G.832
frame or 384 times for each inbound E3/ITU-T G.751 frame. The Receive Pay-
load Data Output Interface block will update the data on the RxNibn[3:0] output
upon the falling edge of these clock signals.
The user is advised to design (or configure) the local terminal equipment to
sample the data on the RxNibn[3:0] output pins, upon the rising edge of these
clock signals.
F2
A25
H2
RxPOHFrame1
RxPOHFrame2
RxPOHFrame3
O
O
O
Receive PLCP Frame POH Serial Output Port - Frame Indicator:
These output pins along with the RxPOH RxPOHClk and RxPOHIns pins com-
prise the Receive PLCP Frame POH Byte serial output port. These output pins
provide framing information to external circuitry receiving and processing this
POH (Path Overhead) data, by pulsing "High" whenever the first bit of the Z6
byte is being output via the RxPOH output pins. These pins are "Low" at all
other times during this PLCP POH Framing cycle.
N
OTE
:
These output pins are only active if the XRT79L73 has been configured
to operate in the ATM/PLCP Modes.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
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