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參數(shù)資料
| 型號(hào)： | XRT79L74 |
| 廠商： | Exar Corporation |
| 英文描述： | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| 中文描述： | 4 -通道DS3/E3自動(dòng)柜員機(jī)用戶到網(wǎng)絡(luò)接口/ Combo IC對(duì)購(gòu)買力平價(jià) |
| 文件頁數(shù)： | 18/70頁 |
| 文件大?。?/td> | 547K |
| 代理商： | XRT79L74 |
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XRT79L74
REV. P1.0.0
PRELIMINARY
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
16
AA3
V24
AD1
W23
TxNib1_1/
Tx8KREF1/
TxHDLCDat1_1
TxNib2_1/
Tx8KREF2/
TxHDLCDat2_1
TxNib3_1/
Tx8KREF3/
TxHDLCDat3_1
TxNib4_1/
Tx8KREF4/
TxHDLCDat4_1
I
I
I
I
Transmit Nibble Input Interface - Bit 1/Transmit PLCP Framing 8kHz Refer-
ence Input/Transmit HDLC Controller Data Bus - Bit 1 Input:
The function of these input pins depend upon whether the XRT79L74 is config-
ured to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Con-
troller Mode, or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxNib_1:
If the XRT79L74 is configured to operate in the Nibble-Parallel Mode, then these
input pins will function as the bit 1 input to the Transmit Nibble-Parallel input
interface. The Transmit Payload Data Input Interface block will sample this sig-
nals (along with TxNibn_0, TxNibn_2 and TxNibn_3) upon the falling edge of
TxNibClk.
N
OTE
:
These input pins are inactive if the XRT79L74 is configured to operate in
the Serial Mode.
ATM/PLCP Mode - Tx8KREF:
If the XRT79L74 is configured to operate in the ATM/PLCP Mode, then the
Transmit PLCP Processor can be configured to synchronize its PLCP frame gen-
eration to these input clock signals. The Transmit PLCP Processor will also use
these input signals to compute the nibble-trailer stuff opportunities.
N
OTE
:
These input pins are inactive if the use has configured the XRT79L74 to
operate in the Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_1:
If the XRT79L74 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. These input pins will function as
Bit 1 within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signals.
AB1
V25
AE1
W24
TxNib1_0/
TxGFC1/
TxHDLCDat1_0
TxNib2_0/
TxGFC2/
TxHDLCDat2_0
TxNib3_0/
TxGFC3/
TxHDLCDat3_0
TxNib4_0/
TxGFC4/
TxHDLCDat4_0
I
I
I
I
Transmit Nibble Interface - Bit 0/Transmit GFC Input pin/Transmit HDLC
Controller Data Bus - Bit 0 Input:
The function of these input pins depend upon whether the XRT79L74 is config-
ured to operate in the Clear-Channel Framer Mode, the High Speed HDLC Con-
troller Mode or in the ATM Mode.
Clear-Channel Framer Mode - TxNib_0:
If the XRT79L74 is configured to operate in the Nibble-Parallel Mode, then these
input pins will function as the bit 0 (LSB) input to the Transmit Nibble-Parallel
input interface. The Transmit Payload Data Input Interface block will sample
these signals (along with TxNibn_1 through TxNibn_3) upon the falling edge of
TxNibClk.
N
OTE
:
These input pins are inactive if the XRT79L74 is configured to operate in
the Serial Mode.
ATM Mode - TxGFC:
These signals, along with TxGFCMSB, and TxGFCClk combine to function as
the Transmit GFC Nibble Field serial input port. The user will specify the value of
the GFC field, within a given ATM cell, by serially transmitting its four bit-value
into these input pins. Each of these four bits will be clocked into the port upon
the rising edge of the TxGFCClk output signals.
High-Speed HDLC Controller Mode - TxHDLCDat_0:
If the XRT79L74 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. These input pins will function as
Bit 0 (the LSB) within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signals.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT79L74IB | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000ID | Clock Synchronizer/Adapter for Communications |
| XRT8000 | Clock Synchronizer/Adapter for Communications(用于通訊的時(shí)鐘同步設(shè)備/調(diào)整器) |
| XRT8001 | WAN Clock for T1 and E1 Systems |
| XRT8001ID | WAN Clock for T1 and E1 Systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT79L74IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000D | 制造商:EXAR 制造商全稱:EXAR 功能描述:CLOCK SYNCHRONIZER/ADAPTER FOR COMMUNICATIONS |
| XRT8000ES | 功能描述:鎖相環(huán) - PLL WAN CLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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