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參數(shù)資料
| 型號： | XRT79L74 |
| 廠商： | Exar Corporation |
| 英文描述： | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| 中文描述： | 4 -通道DS3/E3自動柜員機用戶到網(wǎng)絡接口/ Combo IC對購買力平價 |
| 文件頁數(shù)： | 20/70頁 |
| 文件大小： | 547K |
| 代理商： | XRT79L74 |
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XRT79L74
REV. P1.0.0
PRELIMINARY
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
18
C7
TxUPrty/
TxPPrty
I
Transmit UTOPIA Data Bus - Parity Input/Transmit POS-PHY Interface - Par-
ity Input:
The function of this input pin depends upon whether the XRT79L74 has been
configured to operate in the ATM UNI or PPP Mode.
ATM UNI Mode - TxUPrty:
The ATM Layer processor will apply the parity value of the byte or word which is
being applied to the Transmit UTOPIA Data Bus (e.g., TxUData[7:0] or TxU-
Data[15:0]) inputs of the XRT79L74, respectively.
N
OTE
:
This parity value should be computed based upon the odd-parity of the
data applied at the Transmit UTOPIA Data Bus.
The Transmit UTOPIA Interface block within the XRT79L74 will independently
compute an odd-parity value of each byte (or word) that it receives from the ATM
Layer processor and will compare it with the logic level of this input pin.
PPP Mode - TxPPrty:
The Link Layer Processor will apply the parity value of the byte or word which is
being applied to the Transmit POS-PHY Data Bus (e.g., TxPData[7:0] or TxP-
Data[15:0]) inputs of the XRT79L74, respectively.
N
OTE
:
This parity value should be computed based upon the odd-parity of the
data applied to the Transmit POS-PHY Data Bus. The Transmit POS-
PHY Interface block within the XRT79L74 will independently compute an
odd-parity value of each byte (or word) that it receives from the Link
Layer processor and will compare it will the logic level of this input pin.
This input pin is only active if the user has configured the XRT79L74
device to operate in either the ATM UNI or the PPP Mode. The user
should tie this input pin to GND if he/she intends to operate the
XRT79L74 device in either the Clear-Channel Framer or High-Speed
HDLC Controller Modes.
D7
TxUEN/
TxPEN
I
Transmit UTOPIA Interface Block - Write Enable/Transmit POS-PHY Inter-
face - Write Enable:
The exact function of this input pin depends upon whether the XRT79L74 device
has been configured to operate in the ATM UNI or PPP Mode.
ATM UNI Mode Operation - TxUENB* - Transmit UTOPIA Interface - Write
Enable Input pin:
This active-low signal, from the ATM Layer processor enables the data on the
Transmit UTOPIA Data Bus to be latched and written into the TxFIFO on the ris-
ing edge of TxUClk. When this signal is asserted (e.g., pulled to a logic "LOW"
level), then the contents of the byte or word that is present, on the Transmit UTO-
PIA Data Bus (TxUData[15:0]), will be latched into the Transmit UTOPIA Inter-
face block, on the rising edge of TxUClk. When this signal is negated, then the
Transmit UTOPIA Data bus inputs will be tri-stated.
PPP Mode Operation - TxPENB*
This active-low signal, from the Link Layer processor enables the data on the
Transmit POS-PHY Data Bus to latched and be written into the TxFIFO on the
rising edge of TxPClk. When this signal is asserted (e.g., pulled to a logic "LOW"
level), then the contents of the byte or word that is present, on the Transmit POS-
PHY Data Bus (TxPData[15:0]), will be latched into the Transmit POS-PHY Inter-
face block, on the rising edge of TxPClk.When this signal is negated, then the
Transmit POS-PHY Data bus inputs will be tri-stated.
N
OTE
:
This input pin is only active if the XRT79L74 device has been configured
to operate in the ATM UNI or PPP Mode. The user should tie this input
pin to GND if he/she intends to operate the XRT79L74 device in either
the Clear-Channel Framer or High-Speed HDLC Controller Mode.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| XRT79L74IB | 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000ID | Clock Synchronizer/Adapter for Communications |
| XRT8000 | Clock Synchronizer/Adapter for Communications(用于通訊的時鐘同步設備/調(diào)整器) |
| XRT8001 | WAN Clock for T1 and E1 Systems |
| XRT8001ID | WAN Clock for T1 and E1 Systems |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT79L74IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC |
| XRT8000 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000D | 制造商:EXAR 制造商全稱:EXAR 功能描述:CLOCK SYNCHRONIZER/ADAPTER FOR COMMUNICATIONS |
| XRT8000ES | 功能描述:鎖相環(huán) - PLL WAN CLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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