參數(shù)資料
型號: XRT83SL38IB-F
廠商: Exar Corporation
文件頁數(shù): 40/88頁
文件大小: 0K
描述: IC LIU SH T1/E1/J1 OCTAL 225BGA
標準包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT83SL38
43
REV. 1.0.2
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
LOCAL ANALOG LOOP-BACK (ALOOP)
With Local Analog Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog
input of the receiver. External inputs at RTIP/RRING in this mode are ignored while valid transmit data
continues to be sent to the line. Local Analog Loop-Back exercises most of the functional blocks of the
XRT83SL38 including the jitter attenuator which can be selected in either the transmit or receive paths. Local
Analog Loop-Back is shown in Figure 17.
In this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path.
REMOTE LOOP-BACK (RLOOP)
With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is
looped back to the transmit path using RCLK as transmit timing. In this mode transmit clock and data are
ignored, while RCLK and receive data will continue to be available at their respective output pins. Remote
Loop-Back with jitter attenuator selected in the receive path is shown in Figure 18.
FIGURE 17. LOCAL ANALOG LOOP-BACK SIGNAL FLOW
FIGURE 18. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN RECEIVE PATH
Rx
Data &
Clock
Recovery
Decoder
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Tx
Encoder
Timing
Control
JA
TTIP
TRING
RTIP
RRING
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
JA
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