參數(shù)資料
型號: XRT83SL38IB-F
廠商: Exar Corporation
文件頁數(shù): 49/88頁
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 OCTAL 225BGA
標(biāo)準(zhǔn)包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT83SL38
51
REV. 1.0.2
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MICROPROCESSOR REGISTER DESCRIPTIONS
TABLE 19: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION
REGISTER ADDRESS
00000000
00010000
00100000
00110000
01000000
01010000
01100000
01110000
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
R/W
0
D6
Reserved
R/W
D5
RXON_n
Receiver ON: Writing a “1” into this bit location turns on the
Receive Section of channel n. Writing a “0” shuts off the
Receiver Section of channel n.
NOTES:
1.
This bit provides independent turn-off or turn-on
control of each receiver channel.
2.
In Hardware mode all receiver channels are always
on in the TQFP package. In the BGA packace all
receiver channels can be turned on or off together by
applying the appropriate signal to the RXON pin (#
K16).
R/W
0
D4
EQC4_n
Equalizer Control bit 4: This bit together with EQC[3:0] are
used for controlling transmit pulse shaping, transmit line build-
out (LBO) and receive monitoring for either T1 or E1 Modes of
operation.
See
Table 5 for description of Equalizer Control bits.
R/W
0
D3
EQC3_n
Equalizer Control bit 3: See bit D4 description for function of
this bit
R/W
0
D2
EQC2_n
Equalizer Control bit 2: See bit D4 description for function of
this bit
R/W
0
D1
EQC1_n
Equalizer Control bit 1: See bit D4 description for function of
this bit
R/W
0
D0
EQC0_n
Equalizer Control bit 0: See bit D4 description for function of
this bit
R/W
0
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