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參數(shù)資料
型號: XRT83SL38IB-F
廠商: Exar Corporation
文件頁數(shù): 69/88頁
文件大小: 0K
描述: IC LIU SH T1/E1/J1 OCTAL 225BGA
標(biāo)準(zhǔn)包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT83SL38
69
REV. 1.0.2
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 36: MICROPROCESSOR REGISTER #129, BIT DESCRIPTION
REGISTER ADDRESS
10000001
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
D7
Reserved
R/W
0
D6
CLKSEL2
Clock Select Inputs for Master Clock Synthesizer bit 2:
In Host mode, CLKSEL[2:0] are input signals to a programma-
ble frequency synthesizer that can be used to generate a mas-
ter clock from an external accurate clock source according to
the following table;
In Hardware mode, the state of these signals are ignored and
the master frequency PLL is controlled by the corresponding
Hardware
pins.
R/W
0
D5
CLKSEL1
Clock Select inputs for Master Clock Synthesizer bit 1:
See description of bit D6 for function of this bit.
R/W
0
D4
CLKSEL0
Clock Select inputs for Master Clock Synthesizer bit 0:
See description of bit D6 for function of this bit.
R/W
0
D3
MCLKRATE
Master clock Rate Select:
The state of this bit programs the
Master Clock Synthesizer to generate the T1/J1 or E1 clock.
The Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE =
“1”.
R/W
0
D2
RXMUTE
Receive Output Mute:
Writing a “1” to this bit, mutes receive
outputs at RPOS/RDATA and RNEG/LCV pins to a “0” state for
any channel that detects an RLOS condition.
NOTE: RCLK is not muted.
R/W
0
204 8
154 4
MCL KE1
kHz
8
16
56
8
56
64
128
256
128
204 8
154 4
MCL KT1
kH z
154 4
X
154 4
X
2 048
1 544
2 048
CL KOU T/
kHz
1 544
2 048
1 544
2 048
1 544
2 048
1 544
2 048
1 544
2 048
1 544
2 048
1 544
0
1
CL KSEL0
0
1
0
1
0
1
0
CL KSEL1
1
0
1
0
1
0
CL KSEL2
0
1
0
1
0
1
0
154 4
204 8
X
2 048
1 544
0
1
0
1
M CL KRAT E
1
0
1
0
1
0
1
0
1
0
1
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