參數(shù)資料
型號(hào): XRT91L33IGTR-F
廠商: Exar Corporation
文件頁數(shù): 1/16頁
文件大?。?/td> 0K
描述: IC MULTIRATE CDR 20TSSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),時(shí)鐘/頻率同步器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH
輸入: LVDS,LVPECL
輸出: LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
AUG 2008
REV. V1.0.0
FEATURES
Performs clock and data recovery for selectable
data of 622.08 Mbps (STS-12/STM-4) or 155.52
Mbps (STS-3/STM-1) NRZ data
Meets Telcordia, ANSI and ITU-T G.783 and G.825
SDH jitter requirements including T1.105.03 - 2002
SONET Jitter Tolerance specification, and GR-253
CORE, GR-253 ILR SONET Jitter specifications.
Lock output pin monitors data run length and
frequency drift from reference clock
Data is resampled at the output
Active High Signal Detect (SIGD) LVPECL input
Low jitter, high-speed outputs support LVPECL and
low-power LVDS termination
19.44 MHz reference frequency LVTTL input
Low power: 215 mW typical
3.3V power supply
20-pin TSSOP package
Requires one external capacitor
PLL bypass operation facilitates board debug
process
ESD greater than 2kV on all pins
APPLICATIONS
SONET/SDH-based Transmission Systems
Add/Drop Multiplexers
Cross Connect Equipment
ATM and Multi-Service Switches, Routers and
Switch/Routers
DSLAMS
SONET/SDH Test Equipment
DWDM Termination Equipment
GENERAL DESCRIPTION
The XRT91L33 is a fully integrated multirate Clock
and Data Recovery (CDR) device for SONET/SDH
622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/
STM-1 applications. The device provides Clock and
Data Recovery (CDR) function by synchronizing its
on-chip Voltage Controlled Oscillator (VCO) to the
incoming serial scrambled non-return to zero (NRZ)
data stream.
Figure 1 shows the block diagram of
the XRT91L33.
FIGURE 1. BLOCK DIAGRAM OF XRT91L33
RXDOP
RXDON
RXCLKOP
RXCLKON
LOCK
LVDS/LVPECL
Output Drivers
CDR
RECVD-
DATAOUT
RECVD-
CLKOUT
STS-12/3
or
STM-4/1
Clock and Data
Recovery
Differential
Receiver
RXDIP
RXDIN
RXDATAIN
RX LOOP
FILTER
SIGD
LCKTOREFN
1
0
PLL
STS12_MODE
REFCK
19.44 MHz
TEST
Internal
biasing
External
100R
termination
1u F
MUTE
RXDO
CAP+
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