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參數(shù)資料
| 型號(hào)： | XRT91L33IGTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MULTIRATE CDR 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），時(shí)鐘/頻率同步器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | LVDS，LVPECL |
| 輸出： | LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
XRT91L33
4
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
REV. V1.0.0
1.0
PIN DESCRIPTIONS
TABLE 2: PIN DESCRIPTION TABLE
NAME
LEVEL
TYPE
PIN
DESCRIPTION
VDDA
PWR
1
3.3V Power supply
RXDIP
LVDS/PECL
I
2
Positive side of receive data input. The high-speed output clock
(RXCLKOP/N) is recovered from this high-speed differential
inupt data.
RXDIN
LVDS/PECL
I
3
Negative side of receive data input. The high-speed output
clock (RXCLKOP/N) is recovered from this high-speed differen-
tial input data.
VSSA
PWR
4
Ground pin
LOCK
LVPECL
O
5
Active HIGH to indicate that the PLL is locked to serial data
input and valid clock and data are present at the serial outputs
(RXDOP/N and RXCLKOP/N). The LOCK will go inactive under
the following conditions:
If SIGD is set LOW
If LCKTOREFN is set LOW
If the VCO has drifted away from the local reference
clock, REFCK, by more than +/- 500 ppm
STS12_MODE
LVTTL
I
6
STS-12 or STS-3 mode selection.
Set HIGH to select the
STS-12 operation. Set LOW for STS-3 operation
REFCK
LVTTL
I
7
Local 19.44 MHz reference clock input for the CDR. REFCK is
used for the PLL phase adjustment during power up. It also
serves as a stable clock source in the absence of serial input
data.
LCKTOREFN
LVTTL
I
8
Lock to REFCK input. When set LOW, this pin causes the out-
put clock, RXCLKOP/N to be held within +/- 500ppm of the
input reference clock REFCL and forces the RXDOP/N to a low
state.
VSS
PWR
9
Ground pin
VDD
PWR
10
3.3V power supply
RXCLKON
LVDS/
LVPECL
O
11
High-speed clock output, negative.
This clock is recovered
from the receive data input (RXDIP/N) and supports either
LVDS or LVPECL termination
RXCLKOP
LVDS/
LVPECL
O
12
High-speed clock output, positive This clock is recovered from
the receive data input (RXDIP/N) and supports either LVDS or
LVPECL. termination
RXDON
LVDS/
LVPECL
O
13
High-speed output, negative This is the retimed version of the
recovered data stream from RXDIP/N and can be in either LVDS
or LVPECL termination
RXDOP
LVDS/
LVPECL
O
14
High-speed output, positive. This is the retimed version of the
recovered data stream from RXDIP/N and can be in either
LVDS or LVPECL termination
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