參數(shù)資料
型號： XRT91L80_0507
廠商： Exar Corporation
英文描述： 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： 2.488/2.666 Gbps的STS-48/STM-16的SONET / SDH收發(fā)器
文件頁數(shù)： 21/45頁
文件大?。?/td> 359K
代理商： XRT91L80_0507
xr
REV. P1.1.0
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80
19
3.2
When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in
Figure 10 and Table 6.
F
IGURE
10. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
Transmit Parallel Data Input Timing
T
ABLE
6: T
RANSMIT
P
ARALLEL
D
ATA
AND
C
LOCK
I
NPUT
T
IMING
S
PECIFICATION
T
ABLE
7: T
RANSMIT
P
ARALLEL
C
LOCK
O
UTPUT
T
IMING
S
PECIFICATION
3.3
The parallel interface also includes a 4x9 FIFO that can be used to eliminate difficult timing issues between the
input transmit clock and the clock derived from the CMU. The use of the FIFO permits the system to tolerate an
arbitrary amount of delay and jitter between TXPCLKOP/N and TXPCLKIP/N. The FIFO can be initialized
when FIFO_RST is asserted and held "High" for 2 cycles of the TXPCLKOP/N clock. When the FIFO_RST is
de-asserted, it will take 8 to 10 TXPCLKOP/N cycles for the FIFO to flush out. Once the FIFO is centered, the
delay between TXPCLKOP/N and TXPCLKIP/N can decrease or increase up to two periods of the low-speed
clock. Should the delay exceed this amount, the read and write pointers will point to the same Nibble in the
FIFO resulting in a loss of transmitted data (FIFO overflow). In the event of a FIFO overflow, the FIFO control
logic will initiate an OVERFLOW signal that can be used by an external controller to issue a FIFO RESET
signal. The device under the control of the FIFO_AUTORST pin can automatically recover from an overflow
condition. When the FIFO_AUTORST input is set to a "High" level, once an overflow condition is detected, the
Transmit FIFO
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
t
TXPCLKI
Transmit parallel clock input period (622.08 MHz non-FEC rate)
1608
ps
t
TXPCLKI
Transmit parallel clock input period (666.51 MHz FEC rate)
1500
ps
t
TXDI_SU
TXPCLKIP/N "High" to data setup time
300
ps
t
TXDI_HD
TXPCLKIP/N "High" to data hold time
300
ps
TX
DUTY
TXPCLKIP/N Duty Cycle
40
60
%
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
t
TXPCLKO
Transmit parallel clock output period (622.08 MHz non-FEC rate)
1608
ps
t
TXPCLKO
Transmit parallel clock output period (666.51 MHz FEC rate)
1500
ps
TX
DUTY
TXPCLKOP/N Duty Cycle
45
55
%
TXPCLKIP/N
TXDI[15:0]P/N
t
TXDI_SU
t
TXDI_HD
t
TXPCLKI
t
TXPCLKO
TXPCLKOP/N
相關(guān)PDF資料
PDF描述
XRT91L80IB 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L80ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L80IB 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L80IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L81 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
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