參數資料
型號： XRT91L80_0507
廠商： Exar Corporation
英文描述： 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： 2.488/2.666 Gbps的STS-48/STM-16的SONET / SDH收發(fā)器
文件頁數： 4/45頁
文件大小： 359K
代理商： XRT91L80_0507
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
xr
REV. P1.1.0
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
APPLICATIONS...........................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
XRT91L80...................................................................................................................................... 1
FEATURES
......................................................................................................................................................2
PRODUCT ORDERING INFORMATION..................................................................................................2
F
IGURE
2. 196 BGA P
INOUT
OF
THE XRT91L80 (T
OP
V
IEW
).......................................................................................................... 3
T
ABLE
OF
C
ONTENTS
............................................................................................................
I
PIN DESCRIPTIONS ..........................................................................................................4
S
ERIAL
M
ICROPROCESSOR
INTERFACE
............................................................................................................4
H
ARDWARE
COMMON
CONTROL
......................................................................................................................5
T
RANSMITTER
S
ECTION
..................................................................................................................................6
RECEIVER
SECTION
.........................................................................................................................................9
P
OWER
AND
G
ROUND
..................................................................................................................................10
N
O
C
ONNECTS
.............................................................................................................................................11
JTAG..........................................................................................................................................................12
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................13
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 13
1.2 CLOCK INPUT REFERENCE ......................................................................................................................... 13
T
ABLE
1: R
EFERENCE
F
REQUENCY
O
PTIONS
(N
ON
-FEC
AND
FEC M
ODE
)...................................................................................... 13
1.3 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 13
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
F
ORWARD
E
RROR
C
ORRECTION
.................................................................................... 13
2.0 RECEIVE SECTION .............................................................................................................................14
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 14
F
IGURE
4. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
B
LOCK
..................................................................................................................... 14
T
ABLE
2: D
IFFERENTIAL
CML I
NPUT
S
WING
P
ARAMETERS
.............................................................................................................. 14
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
T
ABLE
3: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
.......................................................................................................... 15
2.3 EXTERNAL SIGNAL DETECTION ................................................................................................................. 15
T
ABLE
4: LOSD D
ECLARATION
P
OLARITY
S
ETTING
......................................................................................................................... 16
2.4 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 16
F
IGURE
5. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
SIPO ........................................................................................................................... 16
2.5 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 16
F
IGURE
6. R
ECEIVE
P
ARALLEL
O
UTPUT
I
NTERFACE
B
LOCK
............................................................................................................. 16
2.6 RECEIVE PARALLEL INTERFACE LVDS OPERATION .............................................................................. 17
F
IGURE
7. LVDS
EXTERNAL
BIASING
RESISTORS
............................................................................................................................. 17
2.7 PARALLEL RECEIVE DATA OUTPUT MUTE UPON LOSD ........................................................................ 17
2.8 PARALLEL RECEIVE DATA OUTPUT DISABLE ......................................................................................... 17
2.9 RECEIVE PARALLEL DATA OUTPUT TIMING ............................................................................................ 17
F
IGURE
8. R
ECEIVE
P
ARALLEL
O
UTPUT
T
IMING
.............................................................................................................................. 17
T
ABLE
5: R
ECEIVE
P
ARALLEL
D
ATA
AND
C
LOCK
O
UTPUT
T
IMING
S
PECIFICATIONS
........................................................................... 17
3.0 TRANSMIT SECTION ..........................................................................................................................18
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 18
F
IGURE
9. T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
............................................................................................................... 18
3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 19
F
IGURE
10. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
.............................................................................................................................. 19
T
ABLE
6: T
RANSMIT
P
ARALLEL
D
ATA
AND
C
LOCK
I
NPUT
T
IMING
S
PECIFICATION
............................................................................... 19
T
ABLE
7: T
RANSMIT
P
ARALLEL
C
LOCK
O
UTPUT
T
IMING
S
PECIFICATION
........................................................................................... 19
3.3 TRANSMIT FIFO ............................................................................................................................................. 19
F
IGURE
11. T
RANSMIT
FIFO
AND
S
YSTEM
I
NTERFACE
.................................................................................................................... 20
3.4 FIFO CALIBRATION UPON POWER UP ....................................................................................................... 20
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 20
F
IGURE
12. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
PISO ......................................................................................................................... 20
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 21
T
ABLE
8: C
LOCK
M
ULTIPLIER
U
NIT
P
ERFORMANCE
......................................................................................................................... 21
3.7 LOOP TIMING AND CLOCK CONTROL ........................................................................................................ 21
T
ABLE
9: L
OOP
TIMING
AND
REFERENCE
DE
-
JITTER
CONFIGURATIONS
.............................................................................................. 22
F
IGURE
13. L
OOP
T
IMING
M
ODE
U
SING
AN
E
XTERNAL
C
LEANUP
VCXO.......................................................................................... 22
3.8 EXTERNAL LOOP FILTER ............................................................................................................................. 23
相關PDF資料
PDF描述
XRT91L80IB 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82IB 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
相關代理商/技術參數
參數描述
XRT91L80ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L80IB 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L80IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L81 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*