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參數(shù)資料
| 型號： | XRT91L80_0507 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| 中文描述： | 2.488/2.666 Gbps的STS-48/STM-16的SONET / SDH收發(fā)器 |
| 文件頁數(shù)： | 36/45頁 |
| 文件大?。?/td> | 359K |
| 代理商： | XRT91L80_0507 |
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XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
xr
REV. P1.1.0
34
D4
LOOPBW
CMU Loop Band Width Select
This bit is used to select the bandwidth of the clock multiplier unit
of the transmit path to a narrow or wide band. Use Wide Band for
clean reference signals and Narrow Band for noisy references.
"0" = Wide Band (4x)
"1" = Narrow Band (1x)
R/W
0
D3
VCXO_SEL
VCXO De-Jitter Select
This bit selects either the normal REFCLKP/N or the de-jitter
VCXO_INP/N as a reference clock.
"0" = Normal REFCLKP/N Mode
"1" = De-Jitter VCXO Mode
R/W
0
D2
TXCLKO16DIS
Auxiliary Clock Disable
This bit is used to control the activity of the auxiliary clock.
"0" = TXCLKO16P/N Enabled
"1" = TXCLKO16P/N Disabled
R/W
0
D1
FIFO_
AUTORST
Automatic FIFO Overflow Reset
If this bit is set to "1", the STS-48/STM-16 transceiver will automat-
ically flush the FIFO upon an overflow condition. Upon power-up,
the FIFO should be manually reset by setting FIFO_RST to "1" for
a minimum of 2 TXPCLKOP/N cycles.
"0" = Manual FIFO reset required for Overflow Conditions
"1" = Automatically resets FIFO upon Overflow Detection
R/W
0
D0
FIFO_RST
Manual FIFO Reset
FIFORST should be set to "1" for a minimum of 2 TXPCLKOP/N
cycles after powering up and during manual FIFO reset. After the
FIFO_RST bit is returned "Low," it will take 8 to 10 TXPCLKOP/N
cycles for the FIFO to flush out. Upon an interrupt indication that
the FIFO has an overflow condition, this bit is used to reset or flush
out the FIFO.
"0" = Normal Operation
"1" = Manual FIFO Reset
N
OTE
:
To automatically reset the FIFO, see the FIFO_AUTORST
bit.
R/W
0
T
ABLE
14: M
ICROPROCESSOR
R
EGISTER
0
X
03
H
B
IT
D
ESCRIPTION
C
ONFIGURATION
0 C
ONTROL
R
EGISTER
(0
X
03
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
相關PDF資料 |
PDF描述 |
|---|---|
| XRT91L80IB | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81 | 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82IB | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L80ES | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L80IB | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L80IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L81 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
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