參數(shù)資料
型號(hào)： XRT91L80_0507
廠商： Exar Corporation
英文描述： 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： 2.488/2.666 Gbps的STS-48/STM-16的SONET / SDH收發(fā)器
文件頁(yè)數(shù)： 23/45頁(yè)
文件大?。?/td> 359K
代理商： XRT91L80_0507
xr
REV. P1.1.0
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80
21
3.6
The high-speed serial clock synthesized by the CMU is divided by 4, and is presented to the upstream device
as TXPCLKOP/N clock . The upstream device should use TXPCLKOP/N as its timing source. The upstream
device then generates the TXPCLKIP/N clock that is phase aligned with the transmit data and provides it to the
parallel interface of the transmitter. The data must meet setup and hold times with respect to TXPCLKIP/N.
The XRT91L80 will latch TXDI[3:0]P/N on the rising edge of TXPCLKIP/N. The clock synthesizer uses a PLL
to lock to the differential input reference clock REFCLKP/N. It will then use this reference clock to generate the
2.488/2.666 GHz STS-48/STM-16 serial clock and in addition feed this high-speed synthesized clock to the
PISO. The Retimer will then align the transmit serial data from the PISO with this 2.488/2.666 GHz synthesized
clock to generate the output TXOP/N. REFCLKP/N input can accept a clock from a differential LVPECL crystal
oscillator that has a frequency accuracy better than 20ppm in order for the high-speed transmit serial clock
frequency to have the accuracy required for SONET systems. Table 8 specifies the Clock Multiplier Unit
performance characteristics.
The CMU can also be driven by an optional external VCXO for loop timed or local reference de-jitter
applications. VCXO_INP/N can be connected to the output of a VCXO that can be configured to clean up the
recovered received clock coming from CP_OUT in loop timing mode before being applied to the input of the
transmit CMU as a reference clock. In addition, the internal phase/frequency detector and charge pump,
combined with an external VCXO can alternately be used as a jitter attenuator to de-jitter a noisy system
reference clock such as REFCLKP/N prior to it being used to time the CMU. The following Section 3.7, “Loop
Timing and Clock Control,” on page 21 illustrate the use of this method.
T
ABLE
8: C
LOCK
M
ULTIPLIER
U
NIT
P
ERFORMANCE
Clock Multiplier Unit (CMU) and Re-Timer
Jitter specification is defined using a 12kHz to 20MHz appropriate SONET/SDH filter.
1
Required to meet SONET output frequency stability requirements.
Loop Timing and Clock Control
Two types of loop timing are possible in the XRT91L80.
In the regular loop timing mode (without an external VCXO), loop timing is controlled by the LOOPTM_NOJA
pin. This mode is selected by asserting the LOOPTM_NOJA signal to a "High" level. When the loop timing
mode is activated, the external local reference clock to the input of the CMU is replaced with the 1/16th or the
1/32nd of the high-speed recovered receive clock coming from the CDR. Under this condition both the transmit
and receive sections are synchronized to the recovered receive clock. The normal looptime mode directly locks
the CMU to the recovered receive clock with no external de-jittering.
Loop timing performance can be further improved using an external VCXO-based PLL to clean up the jitter of
the recovered receive clock. In this case the VCXO_SEL pin should be set "High." By doing so, the CMU
receives its reference clock signal from an external VCXO connected to the VCXO_INP/N inputs. The
LOOPTM_JA pin must also be set "High" in order to select the recovered receive clock as the reference source
for the de-jitter PLL. In this state, the VCXO will be phase locked to the recovered receive clock through a
narrowband loop filter. The use of the on-chip phase/frequency detector with charge pump and an external
VCXO to remove the transmit jitter due to jitter in the recovered clock is shown in Figure 13.
3.7
N
AME
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
REF
DUTY
Reference clock duty cycle
45
55
%
REF
TOL
Reference clock frequency tolerance
1
-20
+20
ppm
REF
STS48
Reference clock jitter limits from 12 KHz to 20 MHz
-61
dB
C
OCLK
JIT
Clock output jitter generation with 77.76 MHz reference clock
3.1
4.0
mUI
rms
OCLK
JIT
Clock output jitter generation with 155.52 MHz reference clock
2.5
3.0
mUI
rms
OCLK
FREQ
Frequency output
2.488
2.667
GHz
OCLK
DUTY
Clock output duty cycle
45
55
%
相關(guān)PDF資料
PDF描述
XRT91L80IB 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L80ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L80IB 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L80IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L81 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
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