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參數(shù)資料
| 型號(hào)： | XWM8731EDS |
| 廠商： | Wolfson Microelectronics |
| 元件分類： | Codec |
| 英文描述： | Portable Internet Audion CODEC with Headphone Driver and Programmable Sample Rates |
| 中文描述： | 便攜式互聯(lián)網(wǎng)三極管編解碼器的耳機(jī)驅(qū)動(dòng)器和可編程采樣率 |
| 文件頁數(shù)： | 30/56頁 |
| 文件大?。?/td> | 595K |
| 代理商： | XWM8731EDS |
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WM8731
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 2.0 February 2001
30
The side tone mode and attenuation is selected under software control using the SIDETONE bit as
shown in Table 10. In true side tone the output from the DAC (DACSEL) and line inputs (BYPASS)
should be deselected from the line output block. However, this can also be used to sum the DAC
output, line inputs and microphone inputs together. The microphone boost gain control and
headphone output volume control and mutes are still operational in side tone mode. The maximum
signal at any point in the side tone path must be no greater than 1.0V rms at VDD = 3.3V, to avoid
distortion. This amplitude tracks linearly with AVDD.
DEVICE OPERATION
DEVICE RESETTING
The WM8731 contains a power on reset circuit that resets the internal state of the device to a known
condition. The power on reset is applied as DCVDD powers on and released only after the voltage
level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on
threshold voltage then the power on reset is re-applied. The threshold voltages and associated
hysteresis are shown in the Electrical Characteristics table.
The user also has the ability to reset the device to a known state under software control as shown in
the table below.
REGISTER
ADDRESS
0001111
Reset Register
BIT
LABEL
DEFAULT
DESCRIPTION
8:0
RESET
not reset
Reset Register
Writing 00000000 to register resets
device
Table 11 Software Control of Reset
When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and
released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the
ACK signal (approximately 1 SCLK period, refer to Figure 32).
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system
’
s
Master Clock. To allow WM8731 to be used in a centrally clocked system, the WM8731 is capable of
either generating this system clock itself or receiving it from an external source as will be discussed.
For applications where it is desirable that the WM8731 is the system clock source, then clock
generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input
and XTO output pins (see CRYSTAL OSCILLATOR section).
For applications where a component other than the WM8731 will generate the reference clock, the
external system can be applied directly through the XTI/MCLK input pin with no software
configuration necessary. Note that in this situation, the oscillator circuit of the WM8731 can be safely
powered down to conserve power (see POWER DOWN section).
CORE CLOCK
The WM8731 DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by
software as shown in Table 12 below.
REGISTER
ADDRESS
0001000
Sampling
Control
BIT
LABEL
DEFAULT
DESCRIPTION
6
CLKIDIV2
0
Core Clock divider select
1 = Core Clock is MCLK divided by 2
0 = Core Clock is MCLK
Table 12 Software Control of Core Clock
Having a programmable MCLK divider allows the device to be used in applications where higher
frequency master Clocks are available. For example the device can support 512fs master clocks
whilst fundamentally operating in a 256fs mode.
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| XWM8734EDS/V | 功能描述:接口—CODEC Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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