參數(shù)資料
型號： XWM8731EDS
廠商： Wolfson Microelectronics
元件分類： Codec
英文描述： Portable Internet Audion CODEC with Headphone Driver and Programmable Sample Rates
中文描述： 便攜式互聯(lián)網(wǎng)三極管編解碼器的耳機驅(qū)動器和可編程采樣率
文件頁數(shù)： 6/56頁
文件大?。?/td> 595K
代理商： XWM8731EDS
WM8731
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 2.0 February 2001
6
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
XWM8731EDS
-10 to +70
o
C
28-pin SSOP
1
AVDD
2
AGND
3
MICBIAS
4
VMID
5
MICIN
6
RLINEIN
7
LLINEIN
8
DCVDD
XTO
9
MODE
10
CSB
SDIN
SCLK
XTI/MCLK
15
CLKOUT
DGND
ADCLRC
ADCDAT
DACDAT
DACLRC
BCLK
DBVDD
LHPOUT
HPGND
HPVDD
RHPOUT
LOUT
ROUT
11
12
13
14
16
17
18
19
20
21
22
23
24
25
28
27
26
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NAME
DBVDD
CLKOUT
BCLK
DACDAT
DACLRC
ADCDAT
ADCLRC
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
ROUT
AVDD
AGND
VMID
MICBIAS
MICIN
RLINEIN
LLINEIN
MODE
CSB
TYPE
Supply
Digital Output
Digital Input/Output
Digital Input
Digital Input/Output
Digital Output
Digital Input/Output
Supply
Analogue Output
Analogue Output
Ground
Analogue Output
Analogue Output
Supply
Ground
Analogue Output
Analogue Output
Analogue Input
Analogue Input
Analogue Input
Digital Input
Digital Input
DESCRIPTION
Digital Buffers VDD
Buffered Clock Output
Digital Audio Bit Clock, Pull Down, (see Note 1)
DAC Digital Audio Data Input
DAC Sample Rate Left/Right Clock, Pull Down (see Note 1)
ADC Digital Audio Data Output
ADC Sample Rate Left/Right Clock, Pull Down (see Note 1)
Headphone VDD
Left Channel Headphone Output
Right Channel Headphone Output
Headphone GND
Left Channel Line Output
Right Channel Line Output
Analogue VDD
Analogue GND
Mid-rail reference decoupling point
Electret Microphone Bias
Microphone Input (AC coupled)
Right Channel Line Input (AC coupled)
Left Channel Line Input (AC coupled)
Control Interface Selection, Pull Up (see Note 1)
3-Wire MPU Chip Select/ 2-Wire MPU interface address selection,
active low, Pull up (see Note 1)
3-Wire MPU Data Input / 2-Wire MPU Data Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
Crystal Input or Master Clock Input (MCLK)
Crystal Output
Digital Core VDD
Digital GND
23
24
25
26
27
28
SDIN
SCLK
XTI/MCLK
XTO
DCVDD
DGND
Digital Input/Output
Digital Input
Digital Input
Digital Output
Supply
Ground
Note:
1.
Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power.
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