參數(shù)資料
型號(hào)： Z8018533FSC
廠商： ZILOG INC
元件分類： 微控制器/微處理器
英文描述： SMART PERIPHERAL CONTROLLERS
中文描述： MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 13/95頁(yè)
文件大?。?/td> 484K
代理商： Z8018533FSC
13
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
AC CHARACTERISTICS
(Continued)
Z80185 / Z80195
(20 MHz)
Min
Z80185 / Z80195
(33 MHz)
Min
No.
Symbol Parameter
Max
Max
Units
28a
28b
29
30
31
32
tIOD
tIOD
tIOD2
tIOD3
tINTS
tINTH
PHI Falling to IORQ Falling Delay IOC = 1)
PHI Rising to IORQ Fallin g Delay (IOC =0)
PHI Falling to IORQ Rising Delay
M1 Falling to IORQ Falling Delay
INT Setup Time to PHI Falling
INT Hold Time from PHI Falling
25
25
25
15
15
15
ns
ns
ns
ns
ns
ns
100
20
10
80
15
10
33
34
35
36
37
tNMIW
tBRS
tBRH
tBAD1
tBAD2
NMI Pulse Width
BUSREQ Setup Time to PHI Falling
BUSREQ Hold Time from PHI Falling
PHI Rising to BUSACK Falling Delay
PHI Falling to BUSACK Rising Delay
35
10
10
25
10
10
ns
ns
ns
ns
ns
25
25
15
15
38
39
40
41
42
tBZD
tMEWH
tMEWL
tRFD1
tRFD2
PHI Rising to Bus Floating Delay Time
MREQ Pulse Width (High)
MREQ Pulse Width (Low)
PHI Rising to RFSH Falling Delay
PHI Rising to RFSH Rising Delay
40
30
ns
ns
ns
ns
ns
tcy –15
2tcy –15
tcy –10
2tcy–10
20
20
15
15
43
44
45
46
47
tHAD1
tHAD2
tDRQS
tDRQH
tTOD
PHI Rising to HALT Falling Delay
PHI Rising to HALT Rising Delay
DREQ Setup Time to PHI Rising
DREQ Hold Time from PHI Rising
PHI Falling to Timer Output Delay
15
15
15
15
ns
ns
ns
ns
ns
20
20
15
15
50
75
48
49
50
51
52
tRES
tREH
tOSC
tEXr
tEXf
RESET Setup Time to PHI Falling
RESET Hold Time From PHI Falling
Oscillator Stabilization Time
External Clock Rise Time (EXTAL)
External Clock Fall Time (EXTAL)
40
25
25
15
ns
ns
ms
ns
ns
20
10
10
20
5
5
53
54
55
56
57
tRr
tRf
tIr
tIf
tSTDI
Reset Rise Time
Reset Fall Time
Input Rise Time (Except EXTAL, RESET)
Input Fall Time (Except EXTAL, RESET)
CSIO Transmit Data Delay Time
(Internal Clock Operation)
50
50
50
50
75
50
50
50
50
60
ms
ms
ns
ns
ns
58
tSTDE
CSIO Transmit Data Delay Time
(External Clock Operation)
CSIO Receive Data Setup Time
(Internal Clock Operation)
CSIO Receive Data Hold Time
(Internal Clock Operation)
7.5 tcy +75
7.5 tcy +60
ns
59
tSRSI
75
60
ns
60
tSRHI
75
60
ns
61
tSRSE
CSIO Receive Data Setup Time
(External Clock Operation)
CSIO Receive Data Hold Time
(External Clock Operation)
MREQ Valid to RAMCS and ROMCS Valid Delay
Rising IORQ Valid to Rising IOCS Valid Delay
75
60
ns
62
tSRHE
75
60
ns
63
64
tdCS
tdIOCS
15
10
15
10
ns
ns
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