參數(shù)資料
型號： Z8018533FSC
廠商： ZILOG INC
元件分類： 微控制器/微處理器
英文描述： SMART PERIPHERAL CONTROLLERS
中文描述： MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 27/95頁
文件大小： 484K
代理商： Z8018533FSC
27
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
Z80185 MPU FUNCTIONAL DESCRIPTION
The Z80185 includes a Zilog Z8S180 MPU (Static Z80180
MPU). This allows software code compatibility with exist-
ing Z80/Z180
software code. The following is an overview
of the major functional units of the Z80185.
The MPU portion of the Z80185 is the Z8S180 core with
added features and modifications. The single-channel
EMSCC of the Z80185 is compatible with the Z85233
EMSCC and features additional enhancements for
LocalTalk and the demultiplexing of the /DTR//REQ and
/WT//REQ lines.
Architecture
The Z80185 combines a high performance CPU core with
a variety of system and I/O resources useful in a broad
range of applications. The CPU core consists of four
functional blocks:
I
I
I
I
Clock Generator
Bus State Controller (Dynamic Memory Refresh)
Memory Management Unit (MMU)
Central Processing Unit (CPU).
The integrated I/O resources make up the remaining
functional blocks:
I
I
Direct Memory Access (DMA control—two channels)
Asynchronous Serial Communications Controller
(ASCI, two channels)
Programmable Reload Timers (PRT, two channels)
Clocked Serial I/O
Channel (CSIO)
Enhanced Z85C30 (EMSCC)
Counter/Timer Channels (CTC)
Parallel I/O
Bidirectional Centronics Controller.
I
I
I
I
I
I
I
Clock Generator.
This logic generates the system clock
from either an external crystal or clock input. The external
clock is divided by two, or one if programmed, and is
provided to both internal and external devices.
Bus State Controller.
This logic performs all of the status
and bus control activity associated with both the CPU and
some on-chip peripherals. This includes wait state timing,
reset cycles, DRAM refresh, and DMA bus exchanges.
Interrupt Controller.
This logic monitors and prioritizes
the variety of internal and external interrupts and traps to
provide the correct responses from the CPU. To maintain
compatibility with the Z80 CPU, three different interrupt
modes are supported.
Memory Management Unit.
The MMU allows the user to
“map” the memory used by the CPU (logically only 64
Kbytes) into the 1 Mbyte addressing range supported by
the Z80185. The organization of the MMU object code
maintains compatibility with the Z80 CPU while offering
access to an extended memory space. This is accom-
plished by using an effective “common area-banked area”
scheme.
Central Processing Unit.
The CPU is microcoded to
provide a core that is object-code compatible with the Z80
CPU. It also provides a superset of the Z80 instruction set,
including 8-bit multiply. This core has been modified to
allow many of the instructions to execute in fewer clock
cycles.
DMA Controller.
The DMA controller provides high-speed
transfers between memory and I/O devices. Transfer op-
erations supported are memory-to-memory, memory to or
from I/O, and I/O-to-I/O. Transfer modes supported are
request, burst, and cycle steal. DMA transfers can access
the full 1 Mbyte addressing range with a block length up to
64 Kbytes, and can cross over the 64 Kbytes boundaries.
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