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參數(shù)資料
| 型號(hào)： | Z8018533FSC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SMART PERIPHERAL CONTROLLERS |
| 中文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 75/95頁 |
| 文件大?。?/td> | 484K |
| 代理商： | Z8018533FSC |
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75
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER
(Continued)
Host ECP Forward Mode
1. After a negotiation for ECP mode, “host” software
should remain in Negotiation mode so that it has com-
plete control of the interface, until one of two situations
occurs. If software has data to send, it should optionally
program the DMA channel to provide the data, and then
set this mode. Alternatively, if software has no data to
send and it detects that nPeriphRequest (nFault) has
gone Low, indicating the peripheral is requesting re-
verse transfer, it should set PIA27-20 as inputs, wait 500
ns, drive nReverseRequest (nInit) to Low to indicate a
reverse transfer, and then set Host ECP Reverse mode.
In other words, software should handle all aspects of
ECP mode, other than active data transfer sequences.
2. Setting this mode configures PIA27-20 as outputs re-
gardless of the contents of register E2. On entry to this
mode, the controller sets Idle and DREQ to request a
byte from software or a DMA channel, but these settings
do not cause an interrupt request.
3. If software, or a DMA channel, writes data to the Output
Holding Register while the Input/Output Register is
empty, the controller immediately transfers the byte to
the IOR, clears Idle, and negates DREQ only momen-
tarily, to request another byte.
4. In this mode, the alternate address for the Output
Holding Register allows software to send a “channel
address” or an RLE count value. Such bytes are typi-
cally written by software rather than a DMA channel.
Writing to the alternate address loads the OHR and
clears DREQ, like writing to the primary address, but
clears a ninth bit that is set when software, or a DMA
channel, writes to the primary address. A similar ninth
bit is associated with the Input/Output Register, from
which it drives the HostAck (nAutoFd) line.
5. As each nine bits arrive in the IOR and thus out onto
PIA27-20 and HostAck (nAutoFd), the controller waits
one PHI clock and then drives HostClk (nStrobe) to
Low. It then waits for the peripheral to drive PeriphAck
(Busy) to High, after which it drives HostClk (nStrobe)
back to High. Then it waits for the peripheral to drive
PeriphAck (Busy) back to Low. When this has hap-
pened, if software or a DMA channel has written a new
byte to the Output Holding Register, and thus cleared
DREQ, the controller transfers the byte to the IOR, sets
DREQ again, and returns to the event sequence at the
start of this paragraph. Otherwise, it returns to the event
sequence at the start of paragraph #3. If software, or a
DMA channel, does not provide a new byte for the time
indicated in the PART register, the controller sets the
Idle flag.
6. While this mode is in effect, software should monitor for
the condition "Idle and no more data left to send", and/
or nPeriphRequest (nFault) Low. Host software has
complete freedom as to whether to honor the peripheral’s
reverse request on nFault while it has data to send.
When there is no more data, software can set Host
Negotiation mode to have full control of the interface,
and if requested can drive P1284Active (nSelectIn) to
Low in order to terminate ECP mode, or can set Host
ECP Reverse mode, wait 500 ns, and drive
nReverseRequest (nInit) to Low.
Status interrupts in Host ECP Forward mode include rising
and falling edges on nPeriphRequest (nFault).
相關(guān)PDF資料 |
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| Z8019533FSC | SMART PERIPHERAL CONTROLLERS |
| Z80185 | SMART PERIPHERAL CONTROLLERS |
| Z8018520FSC | SMART PERIPHERAL CONTROLLERS |
| Z80195 | SMART PERIPHERAL CONTROLLERS |
| Z8019520FSC | SMART PERIPHERAL CONTROLLERS |
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