參數(shù)資料
型號(hào): Z8913820FSC
廠商: ZILOG INC
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: 8-BIT, 20.48 MHz, MIXED DSP, PQFP100
封裝: QFP-100
文件頁(yè)數(shù): 32/65頁(yè)
文件大?。?/td> 2054K
代理商: Z8913820FSC
Z89138/Z89139
Voice Processing Controllers
Zilog
38
P R E L I M I N A R Y
DS97TAD0201
Z8 MCU FUNCTIONAL DESCRIPTION (Continued)
SCLK/TCLK divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The pur-
pose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
control) and/or HALT Mode (where TCLK sources
counter/timers and interrupt logic).
Stop-Mode Recovery Source (D4-D2). These three bits
of the SMR specify the wake-up source of the Stop-Mode
Recovery (Figure 27 and Table 8).
Stop-Mode Recovery Delay Select (D5). When Low, this
bit disables the 5 ms /RESET delay after Stop-Mode Re-
covery. The default configuration of this bit is 1. If the “fast”
wake up is selected, the Stop-Mode Recovery source is
kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit po-
sition indicates that a high level on any one of the recovery
sources wakes the Z89138/139 from STOP Mode. A 0 in-
dicates low level recovery. The default is 0 on POR (Table
8).
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. It is active High, and is 0 (cold)
on POR/WDT /RESET. This bit is Read-Only. It is used to
distinguish between a cold or warm start.
Figure 27. Stop-Mode Recovery Source
P31
P32
P33
HSEC
Stop Mode Recovery Edge
Select (SMR)
P33 From Pads
Digital/Analog Mode
Select (P3M)
To P33 Data
Latch and IRQ1
To POR
RESET
SMR
D4 D3 D2
0
VDD
SMR
D4 D3 D2
0
1
0
1
D4 D3 D2
1
0
D4 D3 D2
1
0
1
D4 D3 D2
1
0
D4 D3 D2
1
P20
P23
P20
P27
MUX
Table 8. Stop-Mode Recovery Source
SMR:432
Operation
Description of Action
D4
D3
D2
0
POR and/or external reset recovery
0
1
No effect
0
1
0
P31 transition
0
1
P32 transition
1
0
P33 transition
1
0
1
HSEC
1
0
Logical NOR of P20 through P23
1
Logical NOR of P20 through P27
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