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參數(shù)資料
| 型號(hào)： | Z8913820FSC |
| 廠商： | ZILOG INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 8-BIT, 20.48 MHz, MIXED DSP, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 46/65頁 |
| 文件大?。?/td> | 2054K |
| 代理商： | Z8913820FSC |
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Z89138/Z89139
Voice Processing Controllers
Zilog
50
P R E L I M I N A R Y
DS97TAD0201
DSP IRQ0. This bit defines the source of the DSP IRQ0 in-
terrupt.
D/A_Sampling Rate. This field defines the sampling rate
of the D/A output. It changes the period to Timer3 interrupt
and the maximum possible accuracy of the D/A Sampling
Rate (Table 18).
DSP0. DSP0 is a general-purpose output pin connected to
Bit 6. This bit has no special significance and can be used
to output data by writing to bit 6.
DSP1. DSP1 is a general-purpose output pin connected to
Bit 7. This bit has no special significance and can be used
to output data by writing to bit 7.
Enable A/D. Writing a 0 to this location disables the A/D
converter, a 1 will enable it. A hardware reset forces this
bit to 0.
Conversion Done. This Read-Only flag indicates that the
A/D conversion is complete. Upon reading EXT5 (A/D da-
ta), the Conversion Done flag is cleared.
Start A/D Conversion. Writing a 1 to this location immedi-
ately starts one conversion cycle. If this bit is reset to 0 the
input data is converted upon successive Timer2 time-outs.
A hardware reset forces this bit to 1.
A/D_Sampling Rate. This field defines the sampling rate
of the A/D. It changes the period of Timer2 interrupt (Table
19).
DSP TIMERS
Timer2 is a free running counter that divides the XTAL fre-
quency (20.48 MHz) to support different sampling rates for
the A/D converter. The sampling rate is defined by the An-
alog Control Register. Upon reaching the end of a count,
the timer generates an interrupt request to the DSP.
Analogous to Timer2, Timer3 generates the different sam-
pling rates for the D/A converter. Timer3 also generates an
interrupt request to the DSP upon reaching its final count
value (Figure 37).
Table 18. D/A Data Accuracy
D/A_Sampling Rate
Sampling Rate
Bit 8
20.48 MHz
29.49 MHz
0
16 kHz
8.04 kHz
1
10 kHz
9.6 kHz
Table 19. A/D Sampling Rate
A/D_Sampling Rate
Sampling Rate
Bit 0
20.48 MHz
29.49 MHz
1
16 kHz
0
8 kHz
9.6 kHz
Figure 37. Timer2 and Timer3
OSC
20.48 MHz
Timer2
8, 16 kHz
Timer3
16, 10 kHz
A/D
D/A
Timer2
16, 9.6 kHz
USC
29.49 MHz
Timer3
8.04, 9.6 kHz
A/D
D/A
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相關(guān)代理商/技術(shù)參數(shù) |
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