參數(shù)資料
型號: ZL30121GGG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: SONET/SDH Low Jitter System Synchronizer
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100
封裝: 9 X 9 MM, 0.80 MM PITCH, CABGA-100
文件頁數(shù): 21/30頁
文件大?。?/td> 326K
代理商: ZL30121GGG
ZL30121
Data Sheet
21
Zarlink Semiconductor Inc.
2.0 Software Configuration
The ZL30121 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The
device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s
processor, or it can operate in a manual mode where the system processor controls most of the operation of the
device.
The following table provides a summary of the registers available for status updates and configuration of the device.
.
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description
Type
Miscellaneous Registers
00
id_reg
A5
Chip and version identification and reset ready
indication register
R
01
use_hw_ctrl
00
Allows some functions of the device to be
controlled by hardware pins
R/W
Interrupts
02
ref_fail_isr
FF
Reference failure interrupt service register
R
03
dpll1_isr
70
DPLL1 interrupt service register
Sticky
R
04
dpll2_isr
00
DPLL2 interrupt service register
Sticky
R
05
ref_mon_fail_0
FF
Ref0 and ref1 failure indications
Sticky
R
06
ref_mon_fail_1
FF
Ref2 and ref3 failure indications.
Sticky
R
07
ref_mon_fail_2
FF
Ref4 and ref5 failure indications
Sticky
R
08
ref_mon_fail_3
FF
Ref6 and ref7 failure indications
Sticky
R
09
ref_fail_isr_mask
00
Reference failure interrupt service register
mask
R/W
0A
dpll1_isr_mask
00
DPLL1 interrupt service register mask
R/W
0B
dpll2_isr_mask
00
DPLL2 interrupt service register mask
R/W
0C
ref_mon_fail_mask_0
FF
Control register to mask each failure indicator
for ref0 and ref1
R/W
0D
ref_mon_fail_mask_1
FF
Control register to mask each failure indicator
for ref2 and ref3
R/W
0E
ref_mon_fail_mask_2
FF
Control register to mask each failure indicator
for ref4 and ref5
R/W
Table 5 - Register Map
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