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參數(shù)資料
| 型號： | ZL30121GGG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH Low Jitter System Synchronizer |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, 0.80 MM PITCH, CABGA-100 |
| 文件頁數(shù)： | 8/30頁 |
| 文件大?。?/td> | 326K |
| 代理商： | ZL30121GGG |
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ZL30121
Data Sheet
8
Zarlink Semiconductor Inc.
K1
diff0_en
I
u
Differential Output 0 Enable (LVCMOS, Schmitt Trigger).
When set high, the
differential LVPECL output 0 driver is enabled. When set low, the differential
driver is tristated reducing power consumption. This pin is internally pulled up to
Vdd.
D3
diff1_en
I
u
Differential Output 1 Enable (LVCMOS, Schmitt Trigger).
When set high, the
differential LVPECL output 1 driver is enabled. When set low, the differential
driver is tristated reducing power consumption.This pin is internally pulled up to
Vdd.
Status
H1
dpll1_lock
O
Lock Indicator (LVCMOS).
This is the lock indicator pin for DPLL1. This output
goes high when DPLL1’s output is frequency and phase locked to the input
reference.
J1
dpll1_holdover
O
Holdover Indicator (LVCMOS).
This pin goes high when DPLL1 enters the
holdover mode.
Serial Interface
E2
sck
I
Clock for Serial Interface (LVCMOS).
Serial interface clock.
F1
si
I
Serial Interface Input (LVCMOS).
Serial interface data input pin.
G1
so
O
Serial Interface Output (LVCMOS).
Serial interface data output pin.
E3
cs_b
I
u
Chip Select for Serial Interface (LVCMOS).
Serial interface chip select. This
pin is internally pulled up to Vdd.
G2
int_b
O
Interrupt Pin (LVCMOS).
Indicates a change of device status prompting the
processor to read the enabled interrupt service registers (ISR). This pin is an
open drain, active low and requires an external pulled up to VDD.
APLL Loop Filter
A6
sdh_filter
A
External Analog PLL Loop Filter terminal.
B6
filter_ref0
A
Analog PLL External Loop Filter Reference.
C6
filter_ref1
A
Analog PLL External Loop Filter Reference.
JTAG and Test
J4
tdo
O
Test Serial Data Out (Output).
JTAG serial data is output on this pin on the
falling edge of tck. This pin is held in high impedance state when JTAG scan is
not enabled.
K2
tdi
I
u
Test Serial Data In (Input).
JTAG serial test instructions and data are shifted in
on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it
should be left unconnected.
H4
trst_b
I
u
Test Reset (LVCMOS).
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-
up to ensure that the device is in the normal functional state. This pin is internally
pulled up to Vdd. If this pin is not used then it should be connected to GND.
K3
tck
I
Test Clock (LVCMOS):
Provides the clock to the JTAG test logic. If this pin is not
used then it should be pulled down to GND.
Pin #
Name
I/O
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30122 | SONET/SDH Low Jitter Line Card Synchronizer |
| ZL30122GGG | SONET/SDH Low Jitter Line Card Synchronizer |
| ZL30406 | SONET/SDH Clock Multiplier PLL |
| ZL30406QGC | Digital Multimeter Clamp Battery Size Code:9V; Current Measuring Range:40.00/400.0A; Current Setting AC:400A; Current Setting DC:400A; Resistance Measuring Range:400 Ohm, 4000 - 40 - 400 kOhm; Voltage Measuring Range AC:600 V RoHS Compliant: NA |
| ZL30406QGC1 | SONET/SDH Clock Multiplier PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30121GGG2 | 制造商:Microsemi Corporation 功能描述:PB FREE LOW JITTER SYSTEM SYNCHRONIZER |
| ZL30121GGG2V2 | 制造商:Microsemi Corporation 功能描述:REV 2 PB FREE LOW JITTER SYSTEM SYNCHRO 制造商:Microsemi Corporation 功能描述:REV 2 PB FREE LOW JITTER SYSTEM SYNCHRO - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
| ZL30121GGGV2 | 制造商:Microsemi Corporation 功能描述:LOW JITTER SYSTEM SYNCHRONIZER 制造商:Microsemi Corporation 功能描述:REV 2 LOW JITTER SYSTEM SYNCHRONIZER - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
| ZL30122 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Low Jitter Line Card Synchronizer |
| ZL30122GGG | 制造商:Microsemi Corporation 功能描述:LOW JITTER SYSTEM SYNCHRONIZER 制造商:Microsemi Corporation 功能描述:SONET/SDH LOW JITTER LINE CARD SYNCHRONIZER 64CABGA - Trays 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 64CABGA |
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