參數(shù)資料
型號: ZL30121GGG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: SONET/SDH Low Jitter System Synchronizer
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100
封裝: 9 X 9 MM, 0.80 MM PITCH, CABGA-100
文件頁數(shù): 23/30頁
文件大小: 326K
代理商: ZL30121GGG
ZL30121
Data Sheet
23
Zarlink Semiconductor Inc.
1F
dpll1_modesel
See
Register
Description
Control register for the DPLL1 mode of
operation
R/W
20
dpll1_refsel
00
DPLL1 reference selection or reference
selection status
R/W
21
dpll1_ref_fail_mask
3C
Control register to mask each failure indicator
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
R/W
22
dpll1_wait_to_restore
00
Control register to indicate the time to restore a
previous failed reference
R/W
23
dpll1_ref_rev_ctrl
00
Control register for the ref0 to ref7 enable
revertive signals
R/W
24
dpll1_ref_pri_ctrl_0
10
Control register for the ref0 and ref1 priority
values
R/W
25
dpll1_ref_pri_ctrl_1
32
Control register for the ref2 and ref3 priority
values
R/W
26
dpll1_ref_pri_ctrl_2
54
Control register for the ref4 and re5 priority
values
R/W
27
dpll1_ref_pri_ctrl_3
76
Control register for the ref6 and ref7 priority
values
R/W
28
dpll1_lock_holdover_status
04
DPLL1 lock and holdover status register
R
29
dpll1_pullinrange
03
Control register for the pull-in range
R/W
DPLL2 Control
2A
dpll2_ctrl_0
00
Control register to program the DPLL2: hitless
switching, the phase slope limit and DPLL
enable
R/W
2B
dpll2_ctrl_1
04
Control register to program the DPLL2:
filter_out_en, freq_offset_en, revert enable
R/W
2C
dpll2_modesel
02
Control register to select the mode of operation
of the DPLL2
R/W
2D
dpll2_refsel
00
DPLL2 reference selection or reference
selection status
R/W
2E
dpll2_ref_fail_mask
3C
Control register to mask each failure indicator
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
R/W
2F
dpll2_wait_to_restore
00
Control register to indicate the time to restore a
previous failed reference for the DPLL2 path
R/W
30
dpll2_ref_rev_ctrl
00
Control register for the ref0 to ref7 enable
revertive signals
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description
Type
Table 5 - Register Map (continued)
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