參數(shù)資料
型號： ZL50015
廠商： Zarlink Semiconductor Inc.
英文描述： Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述： 增強1K的數(shù)字交換與地層4E條數(shù)字鎖相環(huán)
文件頁數(shù)： 108/122頁
文件大?。?/td> 926K
代理商： ZL50015
ZL50015
Data Sheet
108
Zarlink Semiconductor Inc.
Figure 42 - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing Diagram
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
-
FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing (Master Mode, Divided Slave Mode, or
Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
FPo0 Output Pulse Width
FPo0 Output Delay from the FPo0 falling edge
to the output frame boundary
FPo0 Output Delay from the output frame
boundary to the FPo0 rising edge
CKo0 Output Clock Period
CKo0 Output High Time
CKo0 Output Low Time
CKo0 Output Rise/Fall Time
t
FPW0
t
FODF0
239
117
244
249
127
ns
ns
C
L
= 30 pF
3
t
FODR0
117
127
ns
4
5
6
7
t
CKP0
t
CKH0
t
CKL0
t
rCK0
, t
fCK0
239
117
117
244
249
127
127
5
ns
ns
ns
ns
C
L
= 30 pF
AC Electrical Characteristics
-
FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
FPo0 Output Pulse Width
FPo0 Output Delay from the FPo0 falling edge
to the output frame boundary
FPo0 Output Delay from the output frame
boundary to the FPo0 rising edge
CKo0 Output Clock Period
CKo0 Output High Time
CKo0 Output Low Time
CKo0 Output Rise/Fall Time
t
FPW0
t
FODF0
218
117
244
270
127
ns
ns
C
L
= 30 pF
3
t
FODR0
97
146
ns
4
5
6
7
t
CKP0
t
CKH0
t
CKL0
t
rCK0
, t
fCK0
218
117
97
244
270
127
146
5
ns
ns
ns
ns
C
L
= 30 pF
t
FPW0
t
FODR0
t
FODF0
FPo0/FPo3
CKo0/CKo3
t
CKL0
t
CKH0
t
CKP0
t
rCK0
t
fCK0
Output Frame Boundary
V
CT
V
CT
相關PDF資料
PDF描述
ZL50015GAC Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015QCC Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015QCC1 Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL
ZL50018GAC 2 K Digital Switch with Enhanced Stratum 3 DPLL
相關代理商/技術參數(shù)
參數(shù)描述
ZL50015_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015GAC 制造商:Microsemi Corporation 功能描述:Switch Fabric 1K x 1K 1.8V/3.3V 256-Pin BGA Tray 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays
ZL50015GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays
ZL50015QCC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256LQFP - Trays
ZL50015QCC1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL
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