參數(shù)資料
型號(hào)： ZL50015
廠商： Zarlink Semiconductor Inc.
英文描述： Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述： 增強(qiáng)1K的數(shù)字交換與地層4E條數(shù)字鎖相環(huán)
文件頁數(shù)： 50/122頁
文件大?。?/td> 926K
代理商： ZL50015
ZL50015
Data Sheet
50
Zarlink Semiconductor Inc.
Test Data Input (TDi)
- Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. The registers are
described in a subsequent section. The received input data is sampled at the rising edge of the TCK pulse.
This pin is internally pulled to high when it is not driven from an external source.
Test Data Output (TDo)
- Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or test data register are serially shifted out towards TDo. The data from TDo is
clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the
TDo driver is set to a high impedance state.
Test Reset (TRST)
- Resets the JTAG scan structure. This pin is internally pulled to high when it is not
driven from an external source.
21.2 Instruction Register
The ZL50015 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a
four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP
Controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data
register path that is used to shift data between TDi and TDo during data register scanning.
21.3 Test Data Registers
As specified in the IEEE-1149.1 standard, the ZL50015 JTAG interface contains three test data registers:
The Boundary-Scan Register
- The Boundary-Scan register consists of a series of boundary-scan cells
arranged to form a scan path around the boundary of the ZL50015 core logic.
The Bypass Register
- The Bypass register is a single stage shift register that provides a one-bit path from
TDi to TDo.
The Device Identification Register
- The JTAG device ID for the ZL50015 is 0C36F14B
H
21.4 BSDL
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE-1149.1 test interface.
Version
<31:28>
0000
Part Number
<27:12>
1100 0011 0110 1111
Manufacturer ID
<11:1>
0001 0100 101
LSB
<0>
1
相關(guān)PDF資料
PDF描述
ZL50015GAC Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015QCC Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015QCC1 Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL
ZL50018GAC 2 K Digital Switch with Enhanced Stratum 3 DPLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50015_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015GAC 制造商:Microsemi Corporation 功能描述:Switch Fabric 1K x 1K 1.8V/3.3V 256-Pin BGA Tray 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays
ZL50015GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays
ZL50015QCC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256LQFP - Trays
ZL50015QCC1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL
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