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參數(shù)資料
| 型號(hào)： | ZL50015 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| 中文描述： | 增強(qiáng)1K的數(shù)字交換與地層4E條數(shù)字鎖相環(huán) |
| 文件頁(yè)數(shù)： | 25/122頁(yè) |
| 文件大小： | 926K |
| 代理商： | ZL50015 |
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ZL50015
Data Sheet
25
Zarlink Semiconductor Inc.
The output timing is dependent on the operation mode that is selected. When the device is in Divided Slave mode,
the frequencies on CKo0 - 3 cannot be greater than the input clock, CKi. For example, if the input clock is
8.192 MHz, the CKo2 pin will not produce a valid output clock and the CKo3 pin can only be programmed to output
a 4.096 MHz or 8.192 MHz clock signal. The output clocks CKo4 - 5 will not generate valid outputs unless the
SLV_DPLLEN (bit 13) of the Control Register (CR) is set.
In Master mode there are programmable output frame pulse, FPo3, and clock pins, CKo3 and CKo4. The outputs
from FPo3 and CKo3 are programmed by the CKOFPO3SEL1 - 0 (bits 13 - 12) in the Output Clock and Frame
Pulse Selection (OCFSR) register. The output clock pin, CKo4, is controlled by setting the CKO4SEL (bit 14) in the
OCFSR register.
In Multiplied Slave mode, CKo4 and CKo5 are not available unless SLV_DPLLEN is set in the Control Register. All
other clocks and frame pulses correspond to the timing shown in Table 3 above.
The device also delivers positive or negative output frame pulse and ST-BUS/GCI-Bus output clock formats via the
programming of various bits in the Output Clock and Frame Pulse Selection Register (OCFSR). By default, the
device delivers the negative output clock format. The ZL50015 can also deliver GCI-Bus format output frame pulses
by programming bits of the Output Clock and Frame Pulse Selection Register (OCFSR). As there is a separate bit
setting for each frame pulse output, some of the outputs can be set to operate in ST-BUS mode and others in
GCI-Bus mode.
The following figures describe the usage of the FPO0P, FPO1P, FPO2P, FPO3P, CKO0P, CKO1P, CKO2P, CKO3P,
CKO4P and CKO5P bits to generate the FPo0 - 3 and CKo0 - 5 timing. FPo_OFF2 is configured to provide the
non-offset frame pulse corresponding to the 19.44 MHz clock on CKo5 by setting the FP19EN (bit 10) in the
FPOFF2 register. In this instance, FPo_OFF2 can be labeled as FPo5.
Pin Name
Output Timing Rate
Output Timing Unit
FPo0 pulse width
244
ns
CKo0
4.096
MHz
FPo1 pulse width
122
ns
CKo1
8.192
MHz
FPo2 pulse width
61
ns
CKo2
16.384
MHz
FPo3 pulse width
244, 122, 61 or 30
ns
CKo3
4.096, 8.192, 16.384 or 32.768
MHz
CKo4
1.544 or 2.048
MHz
FPo5 pulse width
51
ns
CKo5
19.44
MHz
Table 3 - Output Timing Generation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50015GAC | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50015QCC | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50015QCC1 | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50018 | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
| ZL50018GAC | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50015_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50015GAC | 制造商:Microsemi Corporation 功能描述:Switch Fabric 1K x 1K 1.8V/3.3V 256-Pin BGA Tray 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays |
| ZL50015GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays |
| ZL50015QCC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256LQFP - Trays |
| ZL50015QCC1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL |
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