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參數(shù)資料
| 型號(hào)： | ZL50015 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| 中文描述： | 增強(qiáng)1K的數(shù)字交換與地層4E條數(shù)字鎖相環(huán) |
| 文件頁(yè)數(shù)： | 17/122頁(yè) |
| 文件大?。?/td> | 926K |
| 代理商： | ZL50015 |
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ZL50015
Data Sheet
17
Zarlink Semiconductor Inc.
H14, D11
100, 104
FPo_OFF0 - 1
Generated Offset Frame Pulse Outputs 0 to 1 (5 V-Tolerant
Three-state Outputs)
Individually programmable 8 kHz frame pulses, offset from the
output frame boundary by a programmable number of channels.
F15
108
FPo_OFF2
or
FPo5
Generated Offset Frame Pulse Output 2 or 19.44 MHz Frame
Pulse Output (5 V-Tolerant Three-state Output)
As FPo_OFF2, this is an individually programmable 8 kHz frame
pulse, offset from the output frame boundary by a programmable
number of channels.
By programming the FP19EN (bit 10) of FPOFF2 register to high,
this signal becomes FPo5, a non-offset frame pulse corresponding
to the 19.44 MHz clock presented on CKo5. FPo5 is only available
in Master mode or when the SLV_DPLLEN bit in the Control
Register is set high while the device is in one of the slave modes.
B7, C7, B5,
J6, D6, H5
170, 172,
174, 227,
176, 221
CKo0 - 5
ST-BUS/GCI-Bus Clock Outputs 0 to 5 (5 V-Tolerant
Three-state Outputs)
CKo0: 4.096 MHz output clock.
CKo1: 8.192 MHz output clock.
CKo2: 16.384 MHz output clock.
CKo3: 4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
programmable output clock.
CKo4: 1.544 MHz or 2.048 MHz programmable output clock.
CKo5: 19.44 MHz output clock.
See Section 6.0 on page 24 for details. In Divided Slave mode, the
frequency of CKo0 - 3 cannot be higher than input clock (CKi).
CKo4 and CKo5 are only available in Master mode or when the
SLV_DPLLEN bit in the Control Register is set high while the
device is in one of the slave modes.
B10
155
FPi
ST-BUS/GCI-Bus
Schmitt-Triggered Input)
This pin accepts the frame pulse which stays active for 61 ns,
122 ns or 244 ns at the frame boundary. The frame pulse
frequency is 8 kHz. The frame pulse associated with the
highest
input or output
data rate must be applied to this pin when the
device is operating in Divided Slave mode or Master mode. The
exception is if the device is operating in Master mode with
loopback (i.e., CKi_LP is set in the Control Register). In that case,
this input must be tied high or low externally. When the device is
operating in Multiplied Slave mode, the frame pulse associated
with the
highest
input
data rate must be applied to this pin. For all
modes (except Master mode with loopback), if the data rate is
16.384 Mbps, a 61 ns wide frame pulse must be used. By default,
the device accepts a negative frame pulse in ST-BUS format, but it
can accept a positive frame pulse instead if the FPINP bit is set
high in the Control Register (CR). It can accept a GCI-formatted
frame pulse by programming the FPINPOS bit in the Control
Register (CR) to high.
Frame
Pulse
Input
(5 V-Tolerant
PBGA Pin
Number
LQFP Pin
Number
Pin Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50015GAC | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50015QCC | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50015QCC1 | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50018 | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
| ZL50018GAC | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50015_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50015GAC | 制造商:Microsemi Corporation 功能描述:Switch Fabric 1K x 1K 1.8V/3.3V 256-Pin BGA Tray 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays |
| ZL50015GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays |
| ZL50015QCC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256LQFP - Trays |
| ZL50015QCC1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL |
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