- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373785 > ZL50019QCC (ZARLINK SEMICONDUCTOR INC) Enhanced 2 K Digital Switch with Stratum 4E DPLL PDF資料下載
參數(shù)資料
| 型號(hào)： | ZL50019QCC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQFP256 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256 |
| 文件頁(yè)數(shù)： | 35/115頁(yè) |
| 文件大?。?/td> | 866K |
| 代理商： | ZL50019QCC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)當(dāng)前第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)
ZL50019
Data Sheet
35
Zarlink Semiconductor Inc.
11.0 Connection Memory Block Programming
This feature allows for fast initialization of the connection memory after power up.
11.1 Memory Block Programming Procedure
1. Set MBPE (bit 3) in the Control Register (CR) from low to high.
2. Configure BPD2 - 0 (bits 3 - 1) in the Internal Mode Selection (IMS) register to the desired values to be loaded
into CM_L.
3. Start the block programming by setting MBPS (bit 0) in the Internal Mode Selection Register (IMS) high. The val-
ues stored in BPD2 - 0 will be loaded into bits 2 - 0 of all CM_L positions. The remaining CM_L locations (bits 15
- 3) and the programmable values in the CM_H (bits 4 - 0) will be loaded with zero values.
The following tables show the resulting values that are in the CM_L and CM_H connection memory locations.
Note: Bits 15 to 5 are reserved in Connection Memory High and should always be 0.
It takes at least two frame periods (250
μ
s) to complete a block program cycle.
MBPS (bit 0) in the Control Register (CR) will automatically reset to a low position after the block programming
process has completed.
MBPE (bit 3) in the Internal Mode Selection (IMS) register must be cleared from high to low to terminate the block
programming process. This is not an automatic action taken by the device and must be performed manually.
Note
: Once the block program has been initiated, it can be terminated at any time prior to completion by setting
MBPS (bit 0) in the Control Register (CR) or MBPE (bit 3) in the Internal Mode Selection (IMS) register to low. If the
MBPE bit was used to terminate the block programming, the MBPS bit will have to be set low before enabling other
device operations.
12.0 Device Performance in Master Mode and Slave Modes
This device has two main operating modes - Master mode and Slave mode.
If the device is programmed to work in Master mode, it is expected that the input clock and frame pulse will be
supplied from the embedded DPLL, either directly (using loopback mode) or outside the device. Sources and
destinations of the device’s serial input and output data, respectively, have to be synchronized with the device’s
output clock and frame pulse. In Master mode, output clocks and frame pulses are driven by the DPLL and they are
always available with any of the specified frequencies.
In addition to Master mode, there are two main Slave modes: Divided Slave mode and Multiplied Slave mode. If the
device is in Slave mode, output clocks and frame pulses are generated based on CKi and FPi. In Divided Slave
mode, output clocks and frame pulses are directly divided from CKi/FPi; therefore, the output clock rate cannot
exceed the CKi rate. In Multiplied Slave mode, the output clocks and frame pulses are generated from a clock
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
BPD2
BPD1
BPD0
Table 5 - Connection Memory Low After Block Programming
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6 - Connection Memory High After Block Programming
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50022 | Enhanced 4 K Digital Switch with Stratum 4E DPLL |
| ZL50022GAC | Enhanced 4 K Digital Switch with Stratum 4E DPLL |
| ZL50022QCC | Enhanced 4 K Digital Switch with Stratum 4E DPLL |
| ZL50023 | Enhanced 4 K Digital Switch |
| ZL50023GAC | Enhanced 4 K Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50019QCG1 | 制造商:Microsemi Corporation 功能描述:PB FREE 2K WITH+CONVERSION AND S4E DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP |
| ZL50020 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 2 K Digital Switch |
| ZL50020GAC | 制造商:Microsemi Corporation 功能描述:2K WITH RATE CONVERSION - Trays |
| ZL50020GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:Microsemi Corporation 功能描述:TIME SLOT INTERFACE ZL50020GAG2 |
| ZL50020QCC | 制造商:Microsemi Corporation 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。