參數(shù)資料
型號: ZL50019QCC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 2 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝: 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256
文件頁數(shù): 85/115頁
文件大?。?/td> 866K
代理商: ZL50019QCC
ZL50019
Data Sheet
85
Zarlink Semiconductor Inc.
26.1.2 External Clock Oscillator
When an external clock oscillator is used, numerous parameters must be considered. They include absolute
frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.
The output clock should be connected directly (not AC coupled) to the OSCi input of the device, and the OSCo
output should be left open as shown in Figure 22 on page 85. XC is a buffered version of the 20 MHz input clock
connected to the internal circuitry.
Figure 22 - Clock Oscillator Circuit
For applications requiring
±
32 ppm clock accuracy, the following requirements should be met:
Maximum Series Resistance
35
Approximate Drive Level
1 mW
Frequency
20.000 MHz
Tolerance
±
32 ppm
Rise and Fall Time
10 ns
Duty Cycle
40% to 60%
+3.3 V
20 MHz OUT
GND
0.1 uF
+3.3 V
OSCo
OSCi
No Connection
XC
2 K DX
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ZL50020GAC 制造商:Microsemi Corporation 功能描述:2K WITH RATE CONVERSION - Trays
ZL50020GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:Microsemi Corporation 功能描述:TIME SLOT INTERFACE ZL50020GAG2
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