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ZL50019
Data Sheet
68
Zarlink Semiconductor Inc.
Bit
Name
Description
15
R3FML
Reference 3 Multi-period Lower Limit Fail Bit
f the device sets this bit to high, the input REF3 fails the multi-period lower limit check.
(See Table 11, “Multi-Period Hysteresis Limits” on page 41)
14
R3FMU
Reference 3 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the multi-period upper limit
check. (See Table 11, “Multi-Period Hysteresis Limits” on page 41)
13
R3FL
Reference 3 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the single-period lower limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
12
R3FU
Reference 3 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the single-period upper limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
11
R2FML
Reference 2 Multi-period Lower Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the multi-period lower limit check.
(See Table 11, “Multi-Period Hysteresis Limits” on page 41)
10
R2FMU
Reference 2 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the multi-period upper limit
check. (See Table 11, “Multi-Period Hysteresis Limits” on page 41)
9
R2FL
Reference 2 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the single-period lower limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
8
R2FU
Reference 2 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the single-period upper limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
7
R1FML
Reference 1 Multi-period Lower Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the multi-period lower limit check.
(See Table 11, “Multi-Period Hysteresis Limits” on page 41)
6
R1FMU
Reference 1 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the multi-period upper limit
check. (See Table 11, “Multi-Period Hysteresis Limits” on page 41)
5
R1FL
Reference 1 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the single-period lower limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
4
R1FU
Reference 1 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the single-period upper limit
check. (See Table 10, “Values for Single Period Limits” on page 40)
Table 40 - Reference Failure Status Register (RSR) Bits - Read Only
External Read Only Address: 0069
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R3
FML
R3
FMU
R3
FL
R3
FU
R2
FML
R2
FMU
R2
FL
R2
FU
R1
FML
R1
FMU
R1
FL
R1
FU
R0
FML
R0
FMU
R0
FL
R0
FU