參數(shù)資料
型號: ZL50019QCC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 2 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝: 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256
文件頁數(shù): 78/115頁
文件大小: 866K
代理商: ZL50019QCC
ZL50019
Data Sheet
78
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 8
Unused
Reserved
In normal functional mode, these bits
MUST
be set to zero.
7 - 0
ST[n]
BRS7 - 0
Stream[n] BER Receive Start Bits
The binary value of these bits refers to the input channel in which the BER data starts
to be compared.
Note: [n] denotes input stream from 0 - 31.
Table 47 - BER Receiver Start Register [n] (BRSR[n]) Bits
Bit
Name
Description
15 - 9
Unused
Reserved
In normal functional mode, these bits
MUST
be set to zero.
8 - 0
ST[n]
BL8 - 0
Stream[n] BER Length Bits
The binary value of these bits refers to the number of consecutive channels expected
to receive the BER pattern. The maximum number of BER channels is 32, 64, 128 and
256 for the data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps
respectively. The minimum number of BER channels is 1. If these bits are set to zero,
no BER test will be performed.
Note: [n] denotes input stream from 0 - 31.
Table 48 - BER Receiver Length Register [n] (BRLR[n]) Bits
External Read/Write Address: 0300
H
- 031F
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
ST[n]
BRS7
ST[n]
BRS6
ST[n]
BRS5
ST[n]
BRS4
ST[n]
BRS3
ST[n]
BRS2
ST[n]
BRS1
ST[n]
BRS0
External Read/Write Address: 0320
H
- 033F
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
ST[n]
BL8
ST[n]
BL7
ST[n]
BL6
ST[n]
BL5
ST[n]
BL4
ST[n]
BL3
ST[n]
BL2
ST[n]
BL1
ST[n]
BL0
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