參數(shù)資料
型號： ZL50019QCC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Enhanced 2 K Digital Switch with Stratum 4E DPLL
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝： 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256
文件頁數(shù)： 48/115頁
文件大?。?/td> 866K
代理商： ZL50019QCC
ZL50019
Data Sheet
48
Zarlink Semiconductor Inc.
24.0 Detailed Register Description
Bit
Name
Description
15 - 14
Unused
Reserved.
In normal functional mode, these bits
MUST
be set to zero.
13
SLV_
DPLLEN
DPLL Enable in Slave Mode (ignored in Master Mode).
When this bit is low, DPLL is disabled in Slave mode.
When this bit is high and OSC_EN = 1, the DPLL is enabled in Slave mode.
When SLV_DPLLEN is set in Slave mode, CKo[3:0] and FPo[3:0] are generated from
CKi and FPi. CKo[5:4] and FPo[5] are locked to the selected input reference (one of
REF[3:0]). In this mode of operation, the DPLL retains its functionality, including the
generation of the REF_FAIL[3:0] output signals. See Table 7, “ZL50019 Operating
Modes” on page 36 for more details.
12 - 11
OPM1 - 0
Operation Mode.
These bits are used to set the device in Master/Slave operation. Refer to Table 7,
“ZL50019 Operating Modes” on page 36 for more details.
10
CKi_LP
CKi and FPi Loopback (Ignored in Slave mode)
When this bit is low, CKi and FPi are used as input pins.
When this bit is high, CKi and FPi are internally looped back from CKo2 (16.384 MHz)
and FPo2 respectively, and CKi pin and FPi pin should be tied low or high externally;
CKIN1 - 0 (bits 6 - 5) of this register should be programmed to be 00. See Table 7,
“ZL50019 Operating Modes” on page 36 for more details.
9
FPINPOS
Input Frame Pulse (FPi) Position
When this bit is low, FPi straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus)
8
CKINP
Clock Input (CKi) Polarity
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.
7
FPINP
Frame Pulse Input (FPi) Polarity
When this bit is low, the input frame pulse FPi has the negative frame pulse format.
When this bit is high, the input frame pulse FPi has the positive frame pulse format.
6 - 5
CKIN1 - 0
Input Clock (CKi) and Frame Pulse (FPi) Selection
The MODE_4M0 and MODE_4M1 pins, as described in “Pin Description” on page 12,
should also be set to define the input clock mode.
Table 16 - Control Register (CR) Bits
External Read/Write Address: 0000
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
SLV_
DPLLEN
OPM
1
OPM
0
CKi_
LP
FPIN
POS
CKINP
FPINP
CKIN
1
CKIN
0
VAR
EN
MBPE
OSB
MS1
MS0
CKIN1 - 0
FPi Active Period
CKi
00
61 ns
16.384 MHz
01
122 ns
8.192 MHz
10
244 ns
4.096 MHz
11
Reserved
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50019QCG1 制造商:Microsemi Corporation 功能描述:PB FREE 2K WITH+CONVERSION AND S4E DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP
ZL50020 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 2 K Digital Switch
ZL50020GAC 制造商:Microsemi Corporation 功能描述:2K WITH RATE CONVERSION - Trays
ZL50020GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:Microsemi Corporation 功能描述:TIME SLOT INTERFACE ZL50020GAG2
ZL50020QCC 制造商:Microsemi Corporation 功能描述:
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