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參數(shù)資料
| 型號： | TS68230FN |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 43/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230FN |
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SECTION 5
TIMER OPERATION AND APPLICATIONS
SUMMARY
This section describes the programmable options
available, capabilities, and restrictions that apply to
the timer. Programming of the timer control register
is outlined with several examples given.
5.1. TIMER OPERATION
The TS68230 timer can provide several facilities
needed by TS68000 operating systems. It can ge-
nerate periodic interrupts, a square wave, or a single
interrupt after a programmed time period. Also, it
can be used for elapsed time measurement or as a
device watchdog.
The PI/T timer contains a 24-bit synchronous down
counter that is loaded from three 8-bit counter pre-
load registers. The 24-bit counter may be clocked by
the output of a 5-bit (divide-by-32) prescaler or by an
external timer input (TIN). If the prescaler is used, it
may be clocked by the system clock (CLK pin) or by
the TIN external input. The counter signals the oc-
currence of an event primarily through zero detec-
tion. (A zero is when the counter of the 24-bit timer
is equal to zero). This sets the zero detect status
(ZDS) bit in the timer status register. It may be
checked by the processor or may be used to gene-
rate a timer interrupt. The ZDS bit can be reset by
writing a one to the timer status register in that bit po-
sition independent of timer operation.
The general operation of the timer is flexible and ea-
sily programmable. The timer is fully configured and
controlled by programming the 8-bit timer control re-
gister (refer to
4.9 Timer Control Register
(TCR)
for additional information). It controls : 1) the choice
between the port C operation and the timer opera-
tion of three timer pins, 2) whether the counter is loa-
ded from the counter preload register or rolls over
when zero detect is reached, 3) the clock input, 4)
whether the prescaler is used, and 5) whether the
timer is enabled.
5.1.1. RUN/HALT DEFINITION. The overall opera-
tion of the timer is described in terms of the run or
halt states. The control of the current state is deter-
mined by programming the timer control register.
When in the halt state, all of the following occur :
1. The prior content of the counter is not altered and
is reliably readable via the count registers.
2. The prescaler is forced to $1F whether or not it
is used.
3. The ZDS status bit is forced to zero, regardless
of the possible zero contents of the 24-bit coun-
ter.
The run state is characterized by :
1. The counter is clocked by the source program-
med in the timer control register.
2. The counter is not reliably readable.
3. The prescaler is allowed to decrement if pro-
grammed for use.
4. The ZDS status bit is set when the 24-bit counter
transitions from $000001 to $000000.
5.1.2. TIMER RULES. The following is a set of rules
that allow easy application of the timer.
1. Refer to 5.1.1. Run/Halt Definition.
2. When the RESET pin is asserted, all bits of the
timer control register are cleared, configuring the
dual function pins as port C inputs.
3. The contents of the counter preload registers and
counter are not affected by the RESET pin.
4. The count registers provide a direct read data
path from each portion of the 24-bit counter, but
data written to their addresses is ignored. (This
results in a normal bus cycle). These registers
are readable at any time, but their contents are
never latched. Unreliable data may be read when
the timer is in the run state.
5. The counter preload registers are readable and
writable at any time and this occurs inde-
pendently of any timer operation. No protection
mechanisms are provided against ill-timed
writes.
6. The input frequency to the 24-bit counter from the
TIN pin or prescaler output must be between zero
and the input frequency at the CLK pin divided by
eight, regardless of the configuration chosen.
7. For configurations in which the prescaler is used
(with the CLK pin or TIN pin as an input), the
contents of the counter preload register (CPR) is
transferred to the counter the first time that the
prescaler passes from $00 to $1F (rolls over) af-
ter entering the run state. Thereafter, the counter
decrements, rolls over, or is loaded from the
counter preload register each time the prescaler
rolls over.
TS68230
43/61
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