27
16-8
16-9
16-10
16-11
16-12
16-13
Return from BRKCS Instruction Software Interrupt (RETCSB Instruction Operation) ....................
Operations of Non-Maskable Interrupt Request Acknowledgment...................................................
Algorithm of Interrupt Acknowledgment Processing .........................................................................
Context Switching Operation by Generation of an Interrupt Request..............................................
Return from Interrupt that Uses Context Switching by Means of RETCS Instruction .....................
Examples of Processing When Another Interrupt Request
Is Generated During Interrupt Processing .........................................................................................
Examples of Processing of Simultaneously Generated Interrupts ...................................................
Differences in Level 3 Interrupt Acknowledgment According
to Setting of Interrupt Mode Control Register (IMC) .........................................................................
Differences between Vectored Interrupt and Macro Service Processing.........................................
Example of Macro Service Processing Sequence ............................................................................
Operation on Completion of Macro Service ......................................................................................
Basic Configuration of Macro Service Control Word.........................................................................
Format of Macro Service Control Word .............................................................................................
Interrupt Request Generation and Acknowledgment (Unit: Clocks).................................................
391
393
397
398
399
401
404
16-14
16-15
405
406
410
411
412
413
428
16-16
16-17
16-18
16-19
16-20
16-21
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
17-14
17-15
17-16
17-17
17-18
17-19
Format of Memory Expansion Mode Register (MM) .........................................................................
m
PD784044 Memory Map...................................................................................................................
m
PD784046 Memory Map...................................................................................................................
Read Timing (8 Bits) ...........................................................................................................................
Write Timing (8 Bits) ...........................................................................................................................
Read Timing (16 Bits, Even Address Access) ...................................................................................
Write Timing (16 Bits, Even Address Access) ...................................................................................
Read Timing (16 Bits, Odd Address Access) ....................................................................................
Write Timing (16 Bits, Odd Address Access).....................................................................................
Format of Memory Extension Mode Register (MM) ..........................................................................
Format of Programmable Wait Control Register 1 (PWC1)..............................................................
Format of Programmable Wait Control Register 2 (PWC2)..............................................................
Read/Write Timing of Address Wait Function....................................................................................
Format of Port 9 Mode Control Register (PMC9)..............................................................................
Wait Control Spaces ...........................................................................................................................
Read Timing of Access Wait Function ...............................................................................................
Write Timing of Access Wait Function ...............................................................................................
Timing with External Wait Signal........................................................................................................
Format of Bus Width Specification Register (BW) ............................................................................
436
438
440
442
442
443
443
444
444
445
447
449
451
454
455
456
458
460
462
18-1
18-2
18-3
18-4
18-5
18-6
Diagram of Standby Mode Transition ................................................................................................
Diagram of Standby Function Block ..................................................................................................
Standby Control Register (STBC) Format .........................................................................................
Format of Oscillation Stabilization Time Specification Register (OSTS) .........................................
STOP Mode Release by NMI Input....................................................................................................
Example of Address/Data Bus Processing ........................................................................................
465
466
468
470
476
480
LIST OF FIGURES (7/8)
Figure No.
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