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CHAPTER 18 STANDBY FUNCTION
18.3 HALT Mode
18.3.1 HALT mode setting and operating states
The HALT mode is selected by setting (1) the HLT bit of the standby control (STBC) register or clearing (0) the STP bit.
The only writes that can be performed on the STBC are 8-bit data writes by means of a dedicated instruction. HALT
mode setting is therefore performed by means of the “MOV STBC, #byte” instruction.
Caution If a condition that releases the HALT mode comes into effect when the HALT mode is being set, the
HALT mode is not entered, and the next instruction is executed, or a branch to a vectored interrupt
service program is performed. Before this branch execution, the instructions after the HALT mode
setting may be executed for 6 clocks. After restoring from the interrupt service, to execute an
instruction after setting the HALT mode, insert 3 NOP instructions before the instruction. To be sure
to set the HALT mode, take the necessary precautions such as clearing the interrupt request before
setting the HALT mode.
Table 18-1. Operating States in HALT Mode
Clock oscillator
Operating
Internal system clock
Operating
CPU
Operation stopped
Note 1
I/O lines
Retain state prior to HALT mode setting
Peripheral functions
Continue operating
Internal RAM
Retained
Bus lines
AD0 to AD7
High-impedance
AD8 to AD15
Retained
Note 2
A16-A19
RD, LWR, HWR output
High level
ASTB output
Low level
Notes 1.
Macro service processing is executed.
2.
If the fetch address is an external memory address, and is 16-bits wide, AD8 through AD15 go into high-
impedance after the macro service interrupt has been processed.
18.3.2 HALT mode release
HALT mode can be released by the following three sources.
Non-maskable interrupt request
Maskable interrupt request (vectored interrupt/context switching/macro service)
RESET input
Release sources and an outline of operations after release are shown in Table 18-2.