355
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
14.4.3 Baud Rate Generator Operation
The baud rate generator only operates when UART/IOE transmit/receive operations are enabled. The generated baud
rate clock is a signal scaled from the internal clock (f
CLK
) or a signal scaled from the clock input from the external baud rate
input (ASCK) pin.
Caution If a write to the baud rate generator control register (BRGC) is performed during communication, the
generated baud rate clock may be disrupted, preventing normal communication from continuing. The
BRGC should therefore not be written to during communication.
(1) Baud rate clock generation in UART mode
(a) Using internal clock (f
CLK
)
This function is selected by setting (1) bit 0 (SCK) of the asynchronous serial interface mode register (ASIM).
The internal clock (f
CLK
) is scaled by the frequency divider, this signal (f
PRS
) is scaled by the 5-bit counter, and
the signal further divided by 2 is used as the baud rate. The baud rate is given by the following expression:
(Baud rate) =
f
CLK
: Internal system clock frequency
k
: Value set in bit MDL3 to bit MDL0 of BRGC (k = 0 to 14)
n
: Value set in bit TPS3 to bit TPS0 of BRGC (n = 0 to 11)
(b) Using external baud rate input
This function is selected by clearing (0) bit 0 (SCK) of the asynchronous serial interface mode register (ASIM).
When this function is used, bit MDL3 to bit MDL0 of the baud rate generator control register (BRGC) must all
be cleared (0) (k= 0).
Set P34 pin (when used with UART2, set P37 pin) in the control mode by using the port 3 mode control register
(PMC3).
The ASCK pin input clock is scaled by the frequency divider, and the signal obtained by dividing this signal by
32 (f
PRS
) (division by 16 and division by 2) is used as the baud rate. The baud rate is given by the following
expression:
(Baud rate) =
f
ASCK
: ASCK pin input clock frequency
n
: Value set in bit TPS3 to bit TPS0 of BRGC (n = 0 to 11)
When this function is used, a number of baud rates can be generated by one external input clock.
f
CLK
(k + 16) 2
n + 2
f
ASCK
2
n + 6